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[DEV] APLL_VAL_* ratios for the clock freq and stuff

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weedy2887
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(Last edited by weedy2887; 17th February 2013 at 07:40 PM.)
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Default [DEV] APLL_VAL_* ratios for the clock freq and stuff

I've been pouring over the sources for a few kernels and I've lost count of the number of combinations. So can anyone explain this s**t?

Ok so stock:
Code:
#define APLL_VAL_1000	((1 << 31) | (125 << 16) | (3 << 8) | 1)
#define APLL_VAL_800	((1 << 31) | (100 << 16) | (3 << 8) | 1)
OC'ed and supposed to have a bus/gpu OC
Code:
#define APLL_VAL_1320   ((1 << 31) | (330 << 16) | (6 << 8) | 1)
#define APLL_VAL_1100   ((1 << 31) | (275 << 16) | (6 << 8) | 1)
OC without touching the bus, but why does 1300 have a 0?
Code:
#define APLL_VAL_1400	((1 << 31) | (175 << 16) | (3 << 8) | 1)
#define APLL_VAL_1300   ((1 << 31) | (325 << 16) | (6 << 8) | 0)
#define APLL_VAL_1200	((1 << 31) | (150 << 16) | (3 << 8) | 1)
Again a bus OC only this is doing something else completely and this feels wrong.
Code:
#define APLL_VAL_1320	((1 << 31) | (165 << 16) | (3 << 8) | (1))
#define APLL_VAL_1096	((1 << 31) | (137 << 16) | (3 << 8) | (1))
...
s5pv210_set_refresh(DMC1, 220000);
There are more but these are the most common patterns. I haven't been able to find anything but source code when googling so if one of the devs could take a few minutes to explain this I would be grateful.
Thank you for your time.
 
krfoy
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FYI,

Code:
ARMCLK,MDIV,PDIV,SDIV,DIVA2M,DIVHCLKM,DIVPCLKM,DIV G2D,DIVMFC,DIVG3D

(1200 Mhz) "1200 300 6 1 5 5 1 3 3 3"
(1204 Mhz) "1204 301 6 1 6 6 1 3 3 3"
(1208 Mhz) "1208 302 6 1 6 6 1 3 3 3"
(1212 Mhz) "1212 303 6 1 6 6 1 3 3 3"
(1216 Mhz) "1216 304 6 1 6 6 1 3 3 3"
(1220 Mhz) "1220 305 6 1 6 6 1 3 3 3"
(1224 Mhz) "1224 306 6 1 6 6 1 3 3 3"
(1228 Mhz) "1228 307 6 1 6 6 1 3 3 3"
(1232 Mhz) "1232 308 6 1 6 6 1 3 3 3"
(1236 Mhz) "1236 309 6 1 6 6 1 3 3 3"
(1240 Mhz) "1240 310 6 1 6 6 1 3 3 3"
(1244 Mhz) "1244 311 6 1 6 6 1 3 3 3"
(1248 Mhz) "1248 312 6 1 6 6 1 3 3 3"
(1252 Mhz) "1252 313 6 1 6 6 1 3 3 3"
(1256 Mhz) "1256 314 6 1 6 6 1 3 3 3"
(1260 Mhz) "1260 315 6 1 6 6 1 3 3 3"
(1264 Mhz) "1264 316 6 1 6 6 1 3 3 3"
(1268 Mhz) "1268 317 6 1 6 6 1 3 3 3"
(1272 Mhz) "1272 318 6 1 6 6 1 3 3 3"
(1276 Mhz) "1276 319 6 1 6 6 1 3 3 3"
(1280 Mhz) "1280 320 6 1 6 6 1 3 3 3"
(1284 Mhz) "1284 321 6 1 6 6 1 3 3 3"
(1288 Mhz) "1288 322 6 1 6 6 1 3 3 3"
(1292 Mhz) "1292 323 6 1 6 6 1 3 3 3"
(1296 Mhz) "1296 324 6 1 6 6 1 3 3 3"
(1300 Mhz) "1300 325 6 1 6 6 1 3 3 3"
(1304 Mhz) "1304 326 6 1 6 6 1 3 3 3"
(1308 Mhz) "1308 327 6 1 6 6 1 3 3 3"
(1312 Mhz) "1312 328 6 1 6 6 1 3 3 3"
(1316 Mhz) "1316 329 6 1 6 6 1 3 3 3"
(1320 Mhz) "1320 330 6 1 6 6 1 3 3 3"
(1324 Mhz) "1324 331 6 1 6 6 1 3 3 3"
(1328 Mhz) "1328 332 6 1 6 6 1 3 3 3"
(1332 Mhz) "1332 333 6 1 6 6 1 3 3 3"
(1336 Mhz) "1336 334 6 1 6 6 1 3 3 3"
(1340 Mhz) "1340 335 6 1 6 6 1 3 3 3"
(1344 Mhz) "1344 336 6 1 6 6 1 3 3 3"
(1348 Mhz) "1348 337 6 1 6 6 1 3 3 3"
(1352 Mhz) "1352 338 6 1 6 6 1 3 3 3"
(1356 Mhz) "1356 339 6 1 6 6 1 3 3 3"
(1360 Mhz) "1360 340 6 1 6 6 1 3 3 3"
(1364 Mhz) "1364 341 6 1 6 6 1 3 3 3"
(1368 Mhz) "1368 342 6 1 6 6 1 3 3 3"
(1372 Mhz) "1372 343 6 1 6 6 1 3 3 3"
(1376 Mhz) "1376 344 6 1 6 6 1 3 3 3"
(1380 Mhz) "1380 345 6 1 6 6 1 3 3 3"
(1384 Mhz) "1384 346 6 1 6 6 1 3 3 3"
(1388 Mhz) "1388 347 6 1 6 6 1 3 3 3"
(1392 Mhz) "1392 348 6 1 6 6 1 3 3 3"
(1396 Mhz) "1396 349 6 1 6 6 1 3 3 3"
(1400 Mhz) "1400 350 6 1 6 6 1 3 3 3"
(1404 Mhz) "1404 351 6 1 7 7 1 3 3 3"
(1408 Mhz) "1408 352 6 1 7 7 1 3 3 3"
(1412 Mhz) "1412 353 6 1 7 7 1 3 3 3"
(1416 Mhz) "1416 354 6 1 7 7 1 3 3 3"
(1420 Mhz) "1420 355 6 1 7 7 1 3 3 3"
(1424 Mhz) "1424 356 6 1 7 7 1 3 3 3"
(1428 Mhz) "1428 357 6 1 7 7 1 3 3 3"
(1432 Mhz) "1432 358 6 1 7 7 1 3 3 3"
(1436 Mhz) "1436 359 6 1 7 7 1 3 3 3"
(1440 Mhz) "1440 360 6 1 7 7 1 3 3 3"
(1444 Mhz) "1444 361 6 1 7 7 1 3 3 3"
(1448 Mhz) "1448 362 6 1 7 7 1 3 3 3"
(1452 Mhz) "1452 363 6 1 7 7 1 3 3 3"
(1456 Mhz) "1456 364 6 1 7 7 1 3 3 3"
(1460 Mhz) "1460 365 6 1 7 7 1 3 3 3"
(1464 Mhz) "1464 366 6 1 7 7 1 3 3 3"
(1468 Mhz) "1468 367 6 1 7 7 1 3 3 3"
(1472 Mhz) "1472 368 6 1 7 7 1 3 3 3"
(1476 Mhz) "1476 369 6 1 7 7 1 3 3 3"
(1480 Mhz) "1480 370 6 1 7 7 1 3 3 3"
(1484 Mhz) "1484 371 6 1 7 7 1 3 3 3"
(1488 Mhz) "1488 372 6 1 7 7 1 3 3 3"
(1492 Mhz) "1492 373 6 1 7 7 1 3 3 3"
(1496 Mhz) "1496 374 6 1 7 7 1 3 3 3"
(1500 Mhz) "1500 375 6 1 7 7 1 4 4 4"
(1504 Mhz) "1504 376 6 1 7 7 1 4 4 4"
(1508 Mhz) "1508 377 6 1 7 7 1 4 4 4"
(1512 Mhz) "1512 378 6 1 7 7 1 4 4 4"
(1516 Mhz) "1516 379 6 1 7 7 1 4 4 4"
(1520 Mhz) "1520 380 6 1 7 7 1 4 4 4"
(1524 Mhz) "1524 381 6 1 7 7 1 4 4 4"
(1528 Mhz) "1528 382 6 1 7 7 1 4 4 4"
(1532 Mhz) "1532 383 6 1 7 7 1 4 4 4"
(1536 Mhz) "1536 384 6 1 7 7 1 4 4 4"
(1540 Mhz) "1540 385 6 1 7 7 1 4 4 4"
(1544 Mhz) "1544 386 6 1 7 7 1 4 4 4"
(1548 Mhz) "1548 387 6 1 7 7 1 4 4 4"
(1552 Mhz) "1552 388 6 1 7 7 1 4 4 4"
(1556 Mhz) "1556 389 6 1 7 7 1 4 4 4"
(1560 Mhz) "1560 390 6 1 7 7 1 4 4 4"
(1564 Mhz) "1564 391 6 1 7 7 1 4 4 4"
(1568 Mhz) "1568 392 6 1 7 7 1 4 4 4"
(1572 Mhz) "1572 393 6 1 7 7 1 4 4 4"
(1576 Mhz) "1576 394 6 1 7 7 1 4 4 4"
(1580 Mhz) "1580 395 6 1 7 7 1 4 4 4"
(1584 Mhz) "1584 396 6 1 7 7 1 4 4 4"
(1588 Mhz) "1588 397 6 1 7 7 1 4 4 4"
(1592 Mhz) "1592 398 6 1 7 7 1 4 4 4"
(1596 Mhz) "1596 399 6 1 7 7 1 4 4 4"
(1600 Mhz) "1600 400 6 1 7 7 1 4 4 4"
- lRabbit (abev66)

Nexus S | Jelly Bean 4.3 JLS36G | vta2-kernel
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