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[Kernel] ardatdat kernel v1.6b3 [CWM] (2012-04-06)

26th April 2012, 03:02 PM |#81  
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I played once with BLN for Galaxy R without modifying the kernel though. The problem with the stock kernel was that the buttons' backlight couldn't be controlled while the screen was off.
 
 
26th April 2012, 03:18 PM |#82  
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To ardatdat :

Well I have navigate to your kernel src yesterday, I have found that your 3D oc patch in tegra2_clocks.c is not complete.

I have seen that you patched the 3D CLK clock with
PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 0x31E, 400000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_MANUAL_RESET), /* scales with voltage and process_id */

However, for the RATE_LIMIT part, you didn't patch the '3d' CLK rate limit as it is still limited on our board.
RATE_LIMIT("3d", 300000000, 0x04, 0x7, 0x08, 0x0F, 0x10),

So please fix it by either change the value of the rate limit to 400000000 or merge the SKUID into the one with 400000000 please.

btw, I have sent you a PM as well in case you don't watch on this subforum any more.
26th April 2012, 03:48 PM |#83  
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Quote:
Originally Posted by UnknownzD

To ardatdat :

Well I have navigate to your kernel src yesterday, I have found that your 3D oc patch in tegra2_clocks.c is not complete.

I have seen that you patched the 3D CLK clock with
PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 0x31E, 400000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_MANUAL_RESET), /* scales with voltage and process_id */

However, for the RATE_LIMIT part, you didn't patch the '3d' CLK rate limit as it is still limited on our board.
RATE_LIMIT("3d", 300000000, 0x04, 0x7, 0x08, 0x0F, 0x10),

So please fix it by either change the value of the rate limit to 400000000 or merge the SKUID into the one with 400000000 please.

btw, I have sent you a PM as well in case you don't watch on this subforum any more.

Hi buddy, I think you know how to develop a kernel if possible can you make a BLN MOD for Galaxy R because AFAIK it requires some modification to the kernel/ROM ?

Moreover you also have a R (when you get it back from Voodoo dev ) so you can actually test it before uploading. Thanks.
26th April 2012, 04:50 PM |#84  
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Quote:
Originally Posted by UnknownzD

To ardatdat :

Well I have navigate to your kernel src yesterday, I have found that your 3D oc patch in tegra2_clocks.c is not complete.

I have seen that you patched the 3D CLK clock with
PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 0x31E, 400000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_MANUAL_RESET), /* scales with voltage and process_id */

However, for the RATE_LIMIT part, you didn't patch the '3d' CLK rate limit as it is still limited on our board.
RATE_LIMIT("3d", 300000000, 0x04, 0x7, 0x08, 0x0F, 0x10),

So please fix it by either change the value of the rate limit to 400000000 or merge the SKUID into the one with 400000000 please.

btw, I have sent you a PM as well in case you don't watch on this subforum any more.

No worry. I have already patched that in few versions before. By the way, thanks for your prompting
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i9103, kernel, overclock, smooth, under-volt
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