haha, after this may be all you become DEV
for i in $(find . | grep .ko | grep './')
do
echo $i
/home/sarthak/Downloads/Toolchains/arm-eabi-4.4.3/bin/arm-eabi-strip --strip-unneeded $i
done
as it is evident from the first line,i was referring to .ko files AKA modules from ramdisk
for ext4 File System we have to change the mounts in init.rc and recovery.rc too (recovery.rc cn be beglected as CWM by tj is already ext4 supported)!!
So if i flash cwm by tj style my stock rom would be ext4 supported?
Enviado desde mi GT-S5670L usando Tapatalk
service sysinit /system/bin/logwrapper /system/xbin/busybox run-parts /system/etc/init.d
disabled
oneshot
arch/arm/mach-msm/acpuclock.c: In function 'acpuclk_set_div':
arch/arm/mach-msm/acpuclock.c:[COLOR="Red"]444[/COLOR]:9: error: 'a11_div' undeclared (first use in this function)
arch/arm/mach-msm/acpuclock.c:[COLOR="red"]444[/COLOR]:9: note: each undeclared identifier is reported only once for each function it appears in
arch/arm/mach-msm/acpuclock.c:[COLOR="red"]436[/COLOR]:53: warning: unused variable 'all_div'
/* Set proper dividers for the given clock speed. */
static void acpuclk_set_div(const struct clkctl_acpu_speed *hunt_s)
{
uint32_t reg_clkctl, reg_clksel, clk_div, src_sel, [COLOR="Red"][B]a11_div[/B][/COLOR];
reg_clksel = readl(A11S_CLK_SEL_ADDR);
/* AHB_CLK_DIV */
clk_div = (reg_clksel >> 1) & 0x03;
/* CLK_SEL_SRC1NO */
src_sel = reg_clksel & 1;
[COLOR="Red"][B]a11_div[/B][/COLOR]=hunt_s->a11clk_src_div;
if(hunt_s->a11clk_khz>600000) {
a11_div=0;
writel(hunt_s->a11clk_khz/19200, MSM_CLK_CTL_BASE+0x33C);
udelay(50);
}
/*
* If the new clock divider is higher than the previous, then
* program the divider before switching the clock
*/
if (hunt_s->ahbclk_div > clk_div) {
reg_clksel &= ~(0x3 << 1);
reg_clksel |= (hunt_s->ahbclk_div << 1);
writel(reg_clksel, A11S_CLK_SEL_ADDR);
}
/* Program clock source and divider */
reg_clkctl = readl(A11S_CLK_CNTL_ADDR);
reg_clkctl &= ~(0xFF << (8 * src_sel));
reg_clkctl |= hunt_s->a11clk_src_sel << (4 + 8 * src_sel);
reg_clkctl |= hunt_s->a11clk_src_div << (0 + 8 * src_sel);
writel(reg_clkctl, A11S_CLK_CNTL_ADDR);
/* Program clock source selection */
reg_clksel ^= 1;
writel(reg_clksel, A11S_CLK_SEL_ADDR);
/*
* If the new clock divider is lower than the previous, then
* program the divider after switching the clock
*/
if (hunt_s->ahbclk_div < clk_div) {
reg_clksel &= ~(0x3 << 1);
reg_clksel |= (hunt_s->ahbclk_div << 1);
writel(reg_clksel, A11S_CLK_SEL_ADDR);
}
}
Does this command make kernel support init.d ?
service sysinit /system/bin/logwrapper /system/xbin/busybox run-parts /system/etc/init.d
disabled
oneshot
sudo apt-get install git-core gnupg flex bison gperf libsdl-dev libesd0-dev libwxgtk2.6-dev build-essential zip curl libncurses5-dev zlib1g-dev valgrind
cd /home/[COLOR="red"]your username[/COLOR]/android/boot.img-tools
cd /home/[COLOR="Red"]your username[/COLOR]/android/GT-S5830_kernel/kernel
gedit Makefile
CROSS_COMPILE =../../toolchain/arm-eabi-4.4.3/bin/arm-eabi-
CROSS_COMPILE =../arm-2011.03/bin/arm-none-eabi-
cd /home/[COLOR="Red"]your username[/COLOR]/android/boot.img-tools/boot/lib/modules
strings fsr.ko | grep vermagic
vermagic=2.6.35.7-perf-[COLOR="Red"]CL783107[/COLOR] preempt mod_unload ARMv6
CONFIG_LOCALVERSION="-perf"
CONFIG_LOCALVERSION="-perf-[COLOR="Red"]CL783107[/COLOR]"
# File systems
#
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
# CONFIG_EXT2_FS_POSIX_ACL is not set
# CONFIG_EXT2_FS_SECURITY is not set
# CONFIG_EXT2_FS_XIP is not set
# CONFIG_EXT3_FS is not set
[COLOR="Blue"]CONFIG_EXT4_FS=y[/COLOR]
CONFIG_EXT4_USE_FOR_EXT23=y
CONFIG_EXT4_FS_XATTR=y
# CONFIG_EXT4_FS_POSIX_ACL is not set
# CONFIG_EXT4_FS_SECURITY is not set
# CONFIG_EXT4_DEBUG is not set
cd /home/your username/android/boot.img-tools/boot/
# Mounting of /cache
[COLOR="Red"][B]mount ext4 /dev/block/stl14 /cache wait nosuid nodev noatime nodiratime noauto_da_alloc[/B][/COLOR]
mount rfs /dev/stl14 /cache nosuid nodev check=no
# Mounting of system/userdata is moved to 'on emmc' and 'on nand' sections
# We chown/chmod /data again so because mount is run as root + defaults
[COLOR="red"][B]mount ext4 /dev/block/stl13 /data wait nosuid nodev noatime nodiratime noauto_da_alloc[/B][/COLOR]
mount rfs /dev/stl13 /data nosuid nodev check=no
# Mount /system rw first to give the filesystem a chance to save a checkpoint
[COLOR="red"][B]mount ext4 /dev/block/stl12 /system ro wait noatime nodiratime noauto_da_alloc[/B][/COLOR]
mount rfs /dev/stl12 /system ro check=no
static void acpuclk_set_div
static void acpuclk_set_div(const struct clkctl_acpu_speed *hunt_s)
{
uint32_t reg_clkctl, reg_clksel, clk_div, src_sel, [B][COLOR="Blue"]a11_div[/COLOR][/B];
reg_clksel = readl(A11S_CLK_SEL_ADDR);
/* AHB_CLK_DIV */
clk_div = (reg_clksel >> 1) & 0x03;
/* CLK_SEL_SRC1NO */
src_sel = reg_clksel & 1;
[B] [COLOR="blue"] a11_div=hunt_s->a11clk_src_div;
if(hunt_s->a11clk_khz>600000) {
a11_div=0;
writel(hunt_s->a11clk_khz/19200, MSM_CLK_CTL_BASE+0x33C);
udelay(50);
}[/COLOR][/B]
/*
* If the new clock divider is higher than the previous, then
* program the divider before switching the clock
*/
........etc.......
/* 7x27 normal with GSM capable modem - PLL0 and PLL1 swapped */
{ 1, 652800, ACPU_PLL_2, 2, 1, 200000, 2, [COLOR="Blue"][B]7[/B][/COLOR], 160000 },
{ 1, 768000, ACPU_PLL_2, 2, 2, 160000, 2, [COLOR="Blue"][B]7[/B][/COLOR], 160000 },
{ 1, 800000, ACPU_PLL_2, 2, 0, 200000, 3, [COLOR="Blue"][B]7[/B][/COLOR], 122880 },
{ 1, 652800, ACPU_PLL_2, 2, 1, 200000, 2, 7, 160000 },
{ 1, 691200, ACPU_PLL_2, 2, 1, 200000, 2, 7, 160000 },
{ 1, 710400, ACPU_PLL_2, 2, 1, 200000, 2, 7, 160000 },
{ 1, 729600, ACPU_PLL_2, 2, 1, 200000, 2, 7, 160000 },
{ 1, 748800, ACPU_PLL_2, 2, 1, 200000, 2, 7, 160000 },
{ 1, 768000, ACPU_PLL_2, 2, 1, 200000, 2, 7, 160000 },
{ 1, 787200, ACPU_PLL_2, 2, 2, 160000, 2, 7, 160000 },
{ 1, 800000, ACPU_PLL_0, 4, 0, 206400, 3, 7, 122880 },
{ 1, 806400, ACPU_PLL_2, 2, 2, 160000, 2, 7, 160000 },
{ 1, 825600, ACPU_PLL_0, 4, 0, 206400, 3, 7, 122880 },
{ 1, 844800, ACPU_PLL_0, 4, 0, 211200, 3, 7, 122880 },
{ 1, 864000, ACPU_PLL_0, 4, 0, 216000, 3, 7, 122880 },
{ 1, 600000, ACPU_PLL_2, 2, 1, 200000, 2, 7, 122880 },
{ 1, 614400, ACPU_PLL_2, 2, 0, 153600, 3, 6, 122880 },
{ 1, 672000, ACPU_PLL_2, 2, 0, 168000, 3, 6, 122880 },
{ 1, 729600, ACPU_PLL_2, 2, 0, 182400, 3, 7, 122880 },
{ 1, 800000, ACPU_PLL_2, 2, 0, 200000, 3, 7, 122880 },
# CONFIG_MSM_CPU_FREQ_SET_MIN_MAX is not set
CONFIG_MSM_CPU_FREQ_SET_MIN_MAX=y
CONFIG_MSM_CPU_FREQ_MAX=600000
CONFIG_MSM_CPU_FREQ_MIN=245000
IO Schedulers
CONFIG_IOSCHED_VR=y
CONFIG_IOSCHED_SIO=y
CPU Power Management
CONFIG_CPU_FREQ_GOV_BRAZILIANWAX=y
CONFIG_CPU_FREQ_GOV_HOTPLUG=y
CONFIG_CPU_FREQ_GOV_INTERACTIVE=y
CONFIG_CPU_FREQ_GOV_SCARY=y
CONFIG_CPU_FREQ_GOV_LIONHEART=y
CONFIG_CPU_FREQ_GOV_LAZY=y
CONFIG_CPU_FREQ_GOV_SMOOTHASS=y
CONFIG_CPU_FREQ_GOV_SAVAGEDZEN=y
CONFIG_CPU_FREQ_GOV_INTERACTIVEX=y
CONFIG_CPU_FREQ_GOV_LAGFREE=y
CONFIG_CPU_FREQ_GOV_MINMAX=y
CONFIG_CPU_FREQ_GOV_SMARTASS2=y