from our findings
{ 0, 24576,SRC_LPXO, 0, 0, 30720000, 900, VDD_RAW(900) },
{ 0, 61440, PLL_3, 5, 11, 61440000, 900, VDD_RAW(900) },
{ 1, 122880, PLL_3, 5, 5, 61440000, 900, VDD_RAW(900) },
{ 0, 184320, PLL_3, 5, 4, 61440000, 900, VDD_RAW(900) },
{ 1, 245760, PLL_3, 5, 2, 61440000, 900, VDD_RAW(900) },
{ 1, 368640, PLL_3, 5, 1, 122800000, 900, VDD_RAW(900) },
{ 1, 460800, PLL_1, 2, 0, 153600000, 900, VDD_RAW(900) },
{ 1, 576000, PLL_1, 2, 0, 153600000, 950, VDD_RAW(950) },
{ 1, 652800, PLL_1, 2, 0, 153600000, 950, VDD_RAW(950) },
{ 1, 768000, PLL_1, 2, 0, 153600000, 950, VDD_RAW(950) },
{ 1, 806400, PLL_2, 3, 0, UINT_MAX, 1000, VDD_RAW(1000)},
{ 1, 921600, PLL_2, 3, 0, UINT_MAX, 1000, VDD_RAW(1000)},
{ 1, 1024000, PLL_2, 3, 0, UINT_MAX, 1000, VDD_RAW(1000)},
this seems to be the minimum stable for everybody
please test and confirm