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Dell Venue overclocking development!

OP chacona

21st June 2012, 04:56 PM   |  #1  
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Hi all,
I found the way to OC my kernel up. That
Code:
/* kernel/arch/arm/mach-msm/acpuclock-8x50.c */
struct clkctl_acpu_speed {
	unsigned int     use_for_scaling;
	unsigned int     acpuclk_khz;
	int              pll;
	unsigned int     acpuclk_src_sel;
	unsigned int     acpuclk_src_div;
	unsigned int     ahbclk_khz;
	unsigned int     ahbclk_div;
	unsigned int     axiclk_khz;
	unsigned int     sc_core_src_sel_mask;
	unsigned int     sc_l_value;
	int              vdd;
	unsigned long    lpj; /* loops_per_jiffy */
};
What we have to do is:

1. Declare a new struct, that is copied from defaults like this:
Code:
struct clkctl_acpu_speed acpu_freq_tbl_1305[] = {
	{ 0, 19200, ACPU_PLL_TCXO, 0, 0, 0, 0, 14000, 0, 0, 1000},
	{ 0, 128000, ACPU_PLL_1, 1, 5, 0, 0, 14000, 2, 0, 1000},
	{ 1, 245760, ACPU_PLL_0, 4, 0, 0, 0, 29000, 0, 0, 1000},
	/* Update AXI_S and PLL0_S macros if above row numbers change. */
	{ 1, 384000, ACPU_PLL_3, 0, 0, 0, 0, 58000, 1, 0xA, 1000},
	{ 0, 422400, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xB, 1000},
	{ 0, 460800, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xC, 1000},
	{ 0, 499200, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xD, 1050},
	{ 0, 537600, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xE, 1050},
	{ 1, 576000, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xF, 1050},
	{ 0, 614400, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x10, 1075},
	{ 0, 652800, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x11, 1100},
	{ 0, 691200, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x12, 1125},
	{ 0, 729600, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x13, 1150},
	{ 1, 768000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x14, 1150},
	{ 0, 806400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x15, 1175},
	{ 0, 844800, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x16, 1225},
	{ 0, 883200, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x17, 1250},
	{ 0, 921600, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x18, 1300},
	{ 0, 960000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x19, 1300},
	{ 1, 998400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1300},
  { 1, 1036800, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1325},
  { 0, 1075200, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1325},
  { 0, 1113600, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1325},
  { 0, 1152000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1350},
  { 0, 1190400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1350},
  { 1, 1228800, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1375},
  /*
  { 1, 1267200, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1300},
  { 1, 1305600, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1300},
  * */
	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
};
2. Initialize: do the following changes (the commented out line is the former, the normal is my change)
Code:
/*
 * static struct clkctl_acpu_speed *acpu_freq_tbl = acpu_freq_tbl_998; */
static struct clkctl_acpu_speed *acpu_freq_tbl = acpu_freq_tbl_1305;
3. Change static void __init acpu_freq_tbl_fixup(void)
Code:
...
	case 0x00:
		max_acpu_khz = 1228800;
		break;
...
Build it, then you'll done!

My questions: (highly appreciated if anyone can help), about "struct clkctl_acpu_speed" meaning:
  1. Do you know the relationship between the frequency and loops_per_jiffy?
  2. Recommended VDD value (int vdd) with each value of frequency?
  3. unsigned int sc_core_src_sel_mask;: how do we use it effectively?
For testing the idea, I changed the above things, and it works. However, it's better if we can set appropriate values for those fields. Please discuss, your contribution will utilize all the capabilities of this Venue phone!

Change list: http://www.mediafire.com/?zc3sg4i912vk681
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11th July 2012, 04:37 AM   |  #2  
chacona's Avatar
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I found the way myself, seems that noone is interested in such topic!

Quote:
Originally Posted by chacona

Hi all,
I found the way to OC my kernel up. That

Code:
/* kernel/arch/arm/mach-msm/acpuclock-8x50.c */
struct clkctl_acpu_speed {
	unsigned int     use_for_scaling;
	unsigned int     acpuclk_khz;
	int              pll;
	unsigned int     acpuclk_src_sel;
	unsigned int     acpuclk_src_div;
	unsigned int     ahbclk_khz;
	unsigned int     ahbclk_div;
	unsigned int     axiclk_khz;
	unsigned int     sc_core_src_sel_mask;
	unsigned int     sc_l_value;
	int              vdd;
	unsigned long    lpj; /* loops_per_jiffy */
};
What we have to do is:

1. Declare a new struct, that is copied from defaults like this:
Code:
struct clkctl_acpu_speed acpu_freq_tbl_1305[] = {
	{ 0, 19200, ACPU_PLL_TCXO, 0, 0, 0, 0, 14000, 0, 0, 1000},
	{ 0, 128000, ACPU_PLL_1, 1, 5, 0, 0, 14000, 2, 0, 1000},
	{ 1, 245760, ACPU_PLL_0, 4, 0, 0, 0, 29000, 0, 0, 1000},
	/* Update AXI_S and PLL0_S macros if above row numbers change. */
	{ 1, 384000, ACPU_PLL_3, 0, 0, 0, 0, 58000, 1, 0xA, 1000},
	{ 0, 422400, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xB, 1000},
	{ 0, 460800, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xC, 1000},
	{ 0, 499200, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xD, 1050},
	{ 0, 537600, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xE, 1050},
	{ 1, 576000, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xF, 1050},
	{ 0, 614400, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x10, 1075},
	{ 0, 652800, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x11, 1100},
	{ 0, 691200, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x12, 1125},
	{ 0, 729600, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x13, 1150},
	{ 1, 768000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x14, 1150},
	{ 0, 806400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x15, 1175},
	{ 0, 844800, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x16, 1225},
	{ 0, 883200, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x17, 1250},
	{ 0, 921600, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x18, 1300},
	{ 0, 960000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x19, 1300},
	{ 1, 998400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1300},
  { 1, 1036800, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1325},
  { 0, 1075200, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1325},
  { 0, 1113600, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1325},
  { 0, 1152000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1350},
  { 0, 1190400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1350},
  { 1, 1228800, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1375},
  /*
  { 1, 1267200, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1300},
  { 1, 1305600, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1300},
  * */
	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
};
2. Initialize: do the following changes (the commented out line is the former, the normal is my change)
Code:
/*
 * static struct clkctl_acpu_speed *acpu_freq_tbl = acpu_freq_tbl_998; */
static struct clkctl_acpu_speed *acpu_freq_tbl = acpu_freq_tbl_1305;
3. Change static void __init acpu_freq_tbl_fixup(void)
Code:
...
	case 0x00:
		max_acpu_khz = 1228800;
		break;
...
Build it, then you'll done!

My questions: (highly appreciated if anyone can help), about "struct clkctl_acpu_speed" meaning:
  1. Do you know the relationship between the frequency and loops_per_jiffy?
  2. Recommended VDD value (int vdd) with each value of frequency?
  3. unsigned int sc_core_src_sel_mask;: how do we use it effectively?
For testing the idea, I changed the above things, and it works. However, it's better if we can set appropriate values for those fields. Please discuss, your contribution will utilize all the capabilities of this Venue phone!

Change list: http://www.mediafire.com/?zc3sg4i912vk681

11th July 2012, 07:49 AM   |  #3  
prasad12ka4's Avatar
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Quote:
Originally Posted by chacona

Hi all,
I found the way to OC my kernel up. That

Code:
/* kernel/arch/arm/mach-msm/acpuclock-8x50.c */
struct clkctl_acpu_speed {
	unsigned int     use_for_scaling;
	unsigned int     acpuclk_khz;
	int              pll;
	unsigned int     acpuclk_src_sel;
	unsigned int     acpuclk_src_div;
	unsigned int     ahbclk_khz;
	unsigned int     ahbclk_div;
	unsigned int     axiclk_khz;
	unsigned int     sc_core_src_sel_mask;
	unsigned int     sc_l_value;
	int              vdd;
	unsigned long    lpj; /* loops_per_jiffy */
};
What we have to do is:

1. Declare a new struct, that is copied from defaults like this:
Code:
struct clkctl_acpu_speed acpu_freq_tbl_1305[] = {
	{ 0, 19200, ACPU_PLL_TCXO, 0, 0, 0, 0, 14000, 0, 0, 1000},
	{ 0, 128000, ACPU_PLL_1, 1, 5, 0, 0, 14000, 2, 0, 1000},
	{ 1, 245760, ACPU_PLL_0, 4, 0, 0, 0, 29000, 0, 0, 1000},
	/* Update AXI_S and PLL0_S macros if above row numbers change. */
	{ 1, 384000, ACPU_PLL_3, 0, 0, 0, 0, 58000, 1, 0xA, 1000},
	{ 0, 422400, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xB, 1000},
	{ 0, 460800, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xC, 1000},
	{ 0, 499200, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xD, 1050},
	{ 0, 537600, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xE, 1050},
	{ 1, 576000, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xF, 1050},
	{ 0, 614400, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x10, 1075},
	{ 0, 652800, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x11, 1100},
	{ 0, 691200, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x12, 1125},
	{ 0, 729600, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x13, 1150},
	{ 1, 768000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x14, 1150},
	{ 0, 806400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x15, 1175},
	{ 0, 844800, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x16, 1225},
	{ 0, 883200, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x17, 1250},
	{ 0, 921600, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x18, 1300},
	{ 0, 960000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x19, 1300},
	{ 1, 998400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1300},
  { 1, 1036800, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1325},
  { 0, 1075200, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1325},
  { 0, 1113600, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1325},
  { 0, 1152000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1350},
  { 0, 1190400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1350},
  { 1, 1228800, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1375},
  /*
  { 1, 1267200, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1300},
  { 1, 1305600, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1300},
  * */
	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
};
2. Initialize: do the following changes (the commented out line is the former, the normal is my change)
Code:
/*
 * static struct clkctl_acpu_speed *acpu_freq_tbl = acpu_freq_tbl_998; */
static struct clkctl_acpu_speed *acpu_freq_tbl = acpu_freq_tbl_1305;
3. Change static void __init acpu_freq_tbl_fixup(void)
Code:
...
	case 0x00:
		max_acpu_khz = 1228800;
		break;
...
Build it, then you'll done!

My questions: (highly appreciated if anyone can help), about "struct clkctl_acpu_speed" meaning:
  1. Do you know the relationship between the frequency and loops_per_jiffy?
  2. Recommended VDD value (int vdd) with each value of frequency?
  3. unsigned int sc_core_src_sel_mask;: how do we use it effectively?
For testing the idea, I changed the above things, and it works. However, it's better if we can set appropriate values for those fields. Please discuss, your contribution will utilize all the capabilities of this Venue phone!

Change list: http://www.mediafire.com/?zc3sg4i912vk681

Quite interesting!!!!
What does your kernel do apart from overclocking ?
Does it resolve the voice issue in CM 7?
If any advantages kindly suggest
14th July 2012, 02:09 AM   |  #4  
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Hi, recently I have to work using C#, so I have no time to investigate more on CM7. With CM7, currently I notice that there are issues regarding keys such as MUTE, CAMERA, and kernel power issues. What is the voice problem with CM7, could you tell me?
14th July 2012, 02:51 AM   |  #5  
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Quote:
Originally Posted by chacona

Hi, recently I have to work using C#, so I have no time to investigate more on CM7. With CM7, currently I notice that there are issues regarding keys such as MUTE, CAMERA, and kernel power issues. What is the voice problem with CM7, could you tell me?

The voice issue is:
Then someone calls and you answer, other person hears a garbeled voice,
But if you disconnect and recall its working fine
15th July 2012, 01:13 PM   |  #6  
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Quote:
Originally Posted by prasad12ka4

The voice issue is:
Then someone calls and you answer, other person hears a garbeled voice,
But if you disconnect and recall its working fine

Okay, thank you for your information. With the information from The Manii about the Phoenix kernel, I am testing their work to see whether problems in stock kernel are solved or not. I will note this issue to see whether I can fix it. At least, I think we should have a good working kernel first.
5th March 2014, 07:53 AM   |  #7  
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hope we could make it work, would be cool to have it at least at 1.4 to 1.9 or even 2ghz

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