| Name
|
normal addr
|
packed addr
|
comment
|
| GPIOA_Base
|
+ 0x0000
|
+ 0x000
|
| GPIOA_Mask |
+ 0x0000 |
+0x000
|
| GPIOA_Direction |
+ 0x0004 |
+0x002 |
I=0, O=1 .dir
|
| GPIOA_Out |
+ 0x0008 |
+0x004 |
Write here .init
|
| GPIOA_TriggerType |
+ 0x000c |
+0x006 |
E=1
|
| GPIOA_EdgeTrigger |
+ 0x0010 |
+0x008 |
RE=1, FE=0
|
| GPIOA_LevelTrigger |
+ 0x0014 |
+0x00a
|
| GPIOA_SleepMask |
+ 0x0018 |
+0x00c
|
| GPIOA_SleepOut |
+ 0x001c |
+0x00e |
.sleep_out
|
| GPIOA_BattFaultOut |
+ 0x0020 |
+0x010 |
.batt_fault_out
|
| GPIOA_IntStatus |
+ 0x0024 |
+0x012
|
| GPIOA_AltFunction |
+ 0x0028 |
+0x014 |
ALT function .alt_function
|
| GPIOA_SleepConf |
+ 0x002c |
+0x016 |
.sleep_conf
|
| GPIOA_Status |
+ 0x0030 |
+0x018 |
Read here
|
| GPIOB_Base |
+ 0x0100 |
+0x080
|
| GPIOB_Mask |
+ 0x0100 |
+0x080
|
| GPIOA_Direction |
+ 0x0104 |
+0x082 |
I=0, O=1 .dir
|
| GPIOB_Out |
+ 0x0108 |
+0x084 |
Write here .init
|
| GPIOB_TriggerType |
+ 0x010c |
+0x086 |
E=1
|
| GPIOB_EdgeTrigger |
+ 0x0110 |
+0x088 |
RE=1, FE=0
|
| GPIOB_LevelTrigger |
+ 0x0114 |
+0x08a
|
| GPIOB_SleepMask |
+ 0x0118 |
+0x08c
|
| GPIOB_SleepOut |
+ 0x011c |
+0x08e |
.sleep_out
|
| GPIOB_BattFaultOut |
+ 0x0120 |
+0x090 |
.batt_fault_out
|
| GPIOB_IntStatus |
+ 0x0124 |
+0x092
|
| GPIOB_AltFunction |
+ 0x0128 |
+0x094 |
ALT function .alt_function
|
| GPIOB_SleepConf |
+ 0x012c |
+0x096 |
.sleep_conf
|
| GPIOB_Status |
+ 0x0130 |
+0x098 |
Read here
|
| GPIOC_Base |
+ 0x0200 |
+0x100
|
| GPIOC_Mask |
+ 0x0200 |
+0x100
|
| GPIOC_Direction |
+ 0x0204 |
+0x102 |
I=0, O=1 .dir
|
| GPIOC_Out |
+ 0x0208 |
+0x104 |
Write here .init
|
| GPIOC_TriggerType |
+ 0x020c |
+0x106 |
E=1
|
| GPIOC_EdgeTrigger |
+ 0x0210 |
+0x108 |
RE=1, FE=0
|
| GPIOC_LevelTrigger |
+ 0x0214 |
+0x10a
|
| GPIOC_SleepMask |
+ 0x0218 |
+0x10c
|
| GPIOC_SleepOut |
+ 0x021c |
+0x10e |
.sleep_out
|
| GPIOC_BattFaultOut |
+ 0x0220 |
+0x110 |
.batt_fault_out
|
| GPIOC_IntStatus |
+ 0x0224 |
+0x112
|
| GPIOC_AltFunction |
+ 0x0228 |
+0x114 |
ALT function .alt_function
|
| GPIOC_SleepConf |
+ 0x022c |
+0x116 |
.sleep_conf
|
| GPIOC_Status |
+ 0x0230 |
+0x118 |
Read here
|
| GPIOD_Base |
+ 0x0300 |
+0x180
|
| GPIOD_Mask |
+ 0x0300 |
+0x180
|
| GPIOD_Direction |
+ 0x0304 |
+0x182 |
I=0, O=1 .dir
|
| GPIOD_Out |
+ 0x0308 |
+0x184 |
Write here .init
|
| GPIOD_TriggerType |
+ 0x030c |
+0x186 |
E=1
|
| GPIOD_EdgeTrigger |
+ 0x0310 |
+0x188 |
RE=1, FE=0
|
| GPIOD_LevelTrigger |
+ 0x0314 |
+0x18a
|
| GPIOD_SleepMask |
+ 0x0318 |
+0x18c
|
| GPIOD_SleepOut |
+ 0x031c |
+0x18e |
.sleep_out
|
| GPIOD_BattFaultOut |
+ 0x0320 |
+0x190
|
| GPIOD_IntStatus |
+ 0x0324 |
+0x192
|
| GPIOD_AltFunction |
+ 0x0328 |
+0x194 |
ALT function .alt_function
|
| GPIOD_SleepConf |
+ 0x032c |
+0x196 |
.sleep_conf
|
| GPIOD_Status |
+ 0x0330 |
+0x198 |
Read here
|
| SPI_Base |
+ 0x0400 |
+0x200
|
| SPI_Control |
+ 0x0400 |
+0x200 |
|
| SPI_Transmit |
+ 0x0404 |
+0x202 |
|
| SPI_Receive |
+ 0x0408 |
+0x204 |
|
| SPI_IntStatus |
+ 0x040c |
+0x206 |
|
| SPI_Status |
+ 0x0410 |
+0x208 |
|
| PWM0_Base |
+ 0x0500 |
+0x280
|
| PWM0_TimeBase |
+ 0x0500 |
+0x280 |
from ASIC2
|
| PWM0_PeriodTime |
+ 0x0504 |
+0x282 |
from ASIC2
|
| PWM0_DutyTime |
+ 0x0508 |
+0x284 |
from ASIC2
|
| PWM1_Base |
+ 0x0600 |
+0x300
|
| PWM1_TimeBase |
+ 0x0600 |
+0x300 |
from ASIC2
|
| PWM1_PeriodTime |
+ 0x0604 |
+0x302 |
from ASIC2
|
| PWM1_DutyTime |
+ 0x0608 |
+0x304 |
from ASIC2
|
| LED0_Base |
+ 0x0700 |
+0x380
|
| LED0_TimeBase |
+ 0x0700 |
+0x380
|
| LED0_PeriodTime |
+ 0x0704 |
+0x382
|
| LED0_DutyTime |
+ 0x0708 |
+0x384
|
| LED0_AutoStopCount |
+ 0x070c |
+0x386
|
| LED1_Base |
+ 0x0800 |
+0x400
|
| LED1_TimeBase |
+ 0x0800 |
+0x400
|
| LED1_PeriodTime |
+ 0x0804 |
+0x402
|
| LED1_DutyTime |
+ 0x0808 |
+0x404
|
| LED1_AutoStopCount |
+ 0x080c |
+0x406
|
| LED2_Base |
+ 0x0900 |
+0x480
|
| LED2_TimeBase |
+ 0x0900 |
+0x480
|
| LED2_PeriodTime |
+ 0x0904 |
+0x482
|
| LED2_DutyTime |
+ 0x0908 |
+0x484
|
| LED2_AutoStopCount |
+ 0x090c |
+0x486
|
| CLOCK_Base |
+ 0x0a00 |
+0x500
|
| CLOCK_CDEX |
+ 0x0a00 |
+0x500 |
Source,Source,SPI,PWM0,PWM1,LED0,LED1,LED2,SD_HOST,SD_BUS,SMBUS,CONTROL_CX,EX0,EX1
|
| CLOCK_SEL |
+ 0x0a04 |
+0x502 |
SD_HLCK_SEL,SD_BCLK_SEL,CX
|
| INTR_Base |
+ 0x0b00 |
+0x580 |
A,B,C,D,LED0,LED1,LED2,SPI,SMBUS,OWM
|
| INTR_IntMask |
+ 0x0b00 |
+0x580
|
| INTR_PIntStat |
+ 0x0b04 |
+0x582
|
| INTR_IntCPS |
+ 0x0b08 |
+0x584
|
| INTR_IntTBS |
+ 0x0b0c |
+0x586
|
| OWM_Base |
+ 0x0c00 |
+0x600
|
| OWM_CMD |
+ 0x0c00 |
+0x600
|
| OWM_DAT |
+ 0x0c04 |
+0x602
|
| OWM_INTR |
+ 0x0c08 |
+0x604
|
| OWM_INTEN |
+ 0x0c0c |
+0x606
|
| OWM_CLKDIV |
+ 0x0c10 |
+0x608
|
| ? |
+ 0x0d00 |
+0x680 |
Non-existing?
|
| SDHWCTRL_Base |
+ 0x0e00 |
+0x700 |
SUSPEND,CLKSEL,PCLR,LEVCD,LEVWP,SDLED,SDPWR
|
| FlashWP_VPP_ON? |
+ 0x0f00 |
+0x780 |
used for flashing on Himalaya & Universal (1: write, 0: protect ?)
|
| HWPROTECT |
+ 0x1000 |
+0x800 |
HTC-SDIO P/N:30H80028-0
|
| EXTCF_Base |
+ 0x1100 |
+0x880
|
| EXTCF_Select |
+ 0x1100 |
+0x880 |
SMOD0,SMOD1,SMOD2,OWM_EN,OWM_SMB,CF0_SLEEP,CF1_SLEEP,...
|
| EXTCF_Reset |
+ 0x1104 |
+0x882
|
| Name
|
normal addr
|
packed addr
|
comment
|
| SM_CONFIG_Base |
+ 0x0200? |
+0x100 |
Not used on any known hardware
|
| SD_CONFIG_Base |
+ 0x0400 |
+0x200
|
| CONFIG_Command |
+ 0x0408 |
+0x204 |
/* R/W: Command */
|
| SD_CONFIG_Addr0 |
+ 0x0420 |
+0x210 |
/* 9:31 SD Control Register Base Address */
|
| SD_CONFIG_Addr1 |
+ 0x0424 |
+0x212 |
/* 9:31 SD Control Register Base Address */
|
| SD_CONFIG_IntPin |
+ 0x0478 |
+0x23c |
/* R/O: interrupt assigned to pin */
|
| SD_CONFIG_ClkStop |
+ 0x0480 |
+0x240 |
/* Set to 0x1f to clock SD controller, 0 otherwise. */
|
| Gated Clock Control |
+ 0x0482 |
+0x241 |
/* at 0x82 - Gated Clock Control */
|
| SD_CONFIG_ClockMode |
+ 0x0484 |
+0x242 |
/* Control clock of SD controller */
|
| SD_CONFIG_SDHC_PinStatus |
+ 0x0488 |
+0x244 |
/* R/0: read status of SD pins */
|
| SD_CONFIG_SDHC_Power1 |
+ 0x0490 |
+0x248 |
/* Power1 - manual power control */
|
| SD_CONFIG_SDHC_Power1 |
+ 0x0492 |
+0x249 |
/* 0x92 - auto power up after card inserted*/
|
| SD_CONFIG_SDHC_Power3 |
+ 0x0494 |
+0x24a |
/* auto power down when card removed */
|
| SD_CONFIG_SDHC_CardDetect |
+ 0x0498 |
+0x24c |
/* */
|
| SD_CONFIG_SDHC_Slot |
+ 0x04A0 |
+0x250 |
/* R/O: define support slot number */
|
| SD_CONFIG_SDHC_ExtGateClk1 |
+ 0x05e0 |
+0x2f0 |
/* Could be used for gated clock (don't use) */
|
| SD_CONFIG_SDHC_ExtGateClk2 |
+ 0x05e2 |
+0x2f1 |
/* Could be used for gated clock (don't use)*/
|
| SD_CONFIG_SDHC_GPIO_OutAndEnable |
+ 0x05e8 |
+0x2f4 |
/* GPIO Output Reg. , at 0x1EA - GPIO Output Enable Reg.*/
|
| SD_CONFIG_SDHC_GPIO_Status |
+ 0x05ec |
+0x2f6 |
/* GPIO Status Reg.*/
|
| SD_CONFIG_SDHC_ExtGateClk3 |
+ 0x05f0 |
+0x2f8 |
/* Bit 1: double buffer/single buffer*/
|
| |
|
|
|
| SD_CTRL_Base |
+ 0x1000 |
+0x800
|
| SD_CTRL_Cmd |
+0x1000 |
+ 0x800
|
| SD_CTRL_Arg0 |
+0x1008 |
+ 0x804
|
| SD_CTRL_Arg1 |
+0x100c |
+ 0x806
|
| SD_CTRL_StopInternal |
+0x1010 |
+ 0x808
|
| SD_CTRL_TransferSectorCount |
+0x1014 |
+ 0x80a
|
| SD_CTRL_Response0 |
+0x1018 |
+ 0x80c
|
| SD_CTRL_Response1 |
+0x101c |
+ 0x80e
|
| SD_CTRL_Response2 |
+0x1020 |
+ 0x810
|
| SD_CTRL_Response3 |
+0x1024 |
+ 0x812
|
| SD_CTRL_Response4 |
+0x1028 |
+ 0x814
|
| SD_CTRL_Response5 |
+0x102c |
+ 0x816
|
| SD_CTRL_Response6 |
+0x1030 |
+ 0x818
|
| SD_CTRL_Response7 |
+0x1034 |
+ 0x81a
|
| SD_CTRL_CardStatus |
+0x1038 |
+ 0x81c
|
| SD_CTRL_BufferCtrl |
+0x103c |
+ 0x81e
|
| SD_CTRL_IntMaskCard |
+0x1040 |
+ 0x820
|
| SD_CTRL_IntMaskBuffer |
+0x1044 |
+ 0x822
|
| SD_CTRL_CardClockCtrl |
+0x1048 |
+ 0x824
|
| SD_CTRL_MemCardXferDataLen |
+0x104c |
+ 0x826
|
| SD_CTRL_MemCardOptionSetup |
+0x1050 |
+ 0x828
|
| SD_CTRL_ErrorStatus0 |
+0x1058 |
+ 0x82c
|
| SD_CTRL_ErrorStatus1 |
+0x105c |
+ 0x82e
|
| SD_CTRL_DataPort |
+0x1060 |
+ 0x830
|
| SD_CTRL_TransactionCtrl |
+0x1068 |
+ 0x834
|
| SD_CTRL_SoftwareReset |
+0x11c0 |
+ 0x8e0
|
| |
|
|
| SDIO_CTRL_Base |
+ 0x1200 |
+0x900
|
| SDIO_CTRL_Cmd |
+0x1200 |
+ 0x900
|
| SDIO_CTRL_CardPortSel |
+0x1204 |
+ 0x902
|
| SDIO_CTRL_Arg0 |
+0x1208 |
+ 0x904
|
| SDIO_CTRL_Arg1 |
+0x120c |
+ 0x906
|
| SDIO_CTRL_StopInternal |
+0x1210 |
|
|
| SDIO_CTRL_TransferBlockCount |
+0x1214 |
+ 0x90a
|
| SDIO_CTRL_Response0 |
+0x1218 |
+ 0x90c
|
| SDIO_CTRL_Response1 |
+0x121c |
+ 0x90e
|
| SDIO_CTRL_Response2 |
+0x1220 |
+ 0x910
|
| SDIO_CTRL_Response3 |
+0x1224 |
+ 0x912
|
| SDIO_CTRL_Response4 |
+0x1228 |
+ 0x914
|
| SDIO_CTRL_Response5 |
+0x122c |
+ 0x916
|
| SDIO_CTRL_Response6 |
+0x1230 |
+ 0x918
|
| SDIO_CTRL_Response7 |
+0x1234 |
+ 0x91a
|
| SDIO_CTRL_CardStatus |
+0x1238 |
+ 0x91c
|
| SDIO_CTRL_BufferCtrl |
+0x123c |
+ 0x91e
|
| SDIO_CTRL_IntMaskCard |
+0x1240 |
+ 0x920
|
| SDIO_CTRL_IntMaskBuffer |
+0x1244 |
+ 0x922
|
| SDIO_CTRL_CardClockCtrl |
+0x1248 |
|
|
| SDIO_CTRL_CardXferDataLen |
+0x124c |
+ 0x926
|
| SDIO_CTRL_CardOptionSetup |
+0x1250 |
+ 0x928
|
| SDIO_CTRL_ErrorStatus0 |
+0x1254 |
+ 0x92c
|
| SDIO_CTRL_ErrorStatus1 |
+0x1258 |
+ 0x92e
|
| SDIO_CTRL_DataPort |
+0x1260 |
+ 0x930
|
| |
+0x1264 |
|
|
| SDIO_CTRL_TransactionCtrl |
+0x1268 |
+ 0x934
|
| SDIO_CTRL_CardIntCtrl |
+0x126c |
+ 0x936
|
| SDIO_CTRL_ClocknWaitCtrl |
+0x1270 |
+ 0x938
|
| SDIO_CTRL_HostInformation |
+0x1274 |
+ 0x93a
|
| SDIO_CTRL_ErrorCtrl |
+0x1278 |
+ 0x93c
|
| SDIO_CTRL_LEDCtrl |
+0x127c |
+ 0x93e
|
| |
|
|
|
| SDIO_CTRL_SoftwareReset |
+0x13c0 |
+ 0x9e0
|
| |
+0x13c4 |
|
|
| |
|
|