*[31-OCT]*[SuperSonic]*[Kernel] HP Pro SuperSonic SR4R SNAPPY|| FLUID || POWERSAVER:

Is SR3 Ready as PreSR3 TestBuild?

  • Yes

    Votes: 95 75.4%

  • No

    Votes: 31 24.6%
  • Total voters
    126
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TrymHansen

TrymHansen

Senior Member
Jun 7, 2011
1,108
952
spica1234 said:
mincpu1on is minimum 2nd core cpu activation frequency
and maxcpu1off means during down ramping scaling of frequency at which max freq it starts deactivating 2nd core.
gueste's polling interval is 200ms for mincpu1on and 500ms for maxcpu1off. while mine is 2000ms for mincpu1on and 1000ms for maxcpu1off.
Which kernel you're using?
Click to expand...
Click to collapse
2.6.32.-9HP-2X-Xtreme-SR3-OTFv2.
You can do the experiment easily yourself, you'll find it's true.

EDIT: When I first wrote the app to control the OTF the naming suggested it would be like you say. Now I've come to think of maxcpu1off as "The maximum frequency at which the 2nd core will stay off" (in other words turn it on if above) and mincpu1on as "The minimum frequency at which cpu2 will stay on" (in other words turn off.)
 
Last edited:
spica1234

spica1234

Retired Recognized Developer
Aug 1, 2010
3,081
3,362
India
TrymHansen said:
2.6.32.-9HP-2X-Xtreme-SR3-OTFv2.
You can do the experiment easily yourself, you'll find it's true.

EDIT: When I first wrote the app to control the OTF the naming suggested it would be like you say. Now I've come to think of maxcpu1off as "The maximum frequency at which the 2nd core will stay off" (in other words turn it on if above) and mincpu1on as "The minimum frequency at which cpu2 will stay on" (in other words turn off.)
Click to expand...
Click to collapse

Strange i have not that issue of locked 300 mhz min frequency. are you sure there is nothing left in init.d i mean no previous script which sets frequecy as per screen events on/off?
SR3 or SR3R2? SR3 is tool old and it was removed due to such issue with OTF.
YEs may be SR3 had that issue of 300mhz min frequency locked up which was resolved in SR3R
mincpu1 on : during upscaling at what min frequency it should activate 2nd core eg. 216->1015 upscaling suppost at 800mhz
maxcpu1off: during downscaling at what max frequency it will turn off 2nd core eg. 1015-> 216 downscaling suppost 503mhz
It wont take quick effect like gueste kernel. as his activation time is 200 ms while mine 2000ms(which is default set b y nvidia)
So my kernel for example will wait for 2000ms after cpu pass mincpu1on frequency after 2000ms still max ramping frequency is 800 then only it activates. suppost if after 2000ms cpu frequency has fall down then it wont activate. same for maxcpu1off

Please find SR3R version latest stable build from below link. thanks to superskill for uploading

http://xdaforums.com/showpost.php?p=24926178&postcount=4623
 
Last edited:
spica1234

spica1234

Retired Recognized Developer
Aug 1, 2010
3,081
3,362
India
Testbuild11: (OC)

-Scheduler tracing support. When launching new process. Scheduler trace cfs rq load. And decide priority for new process. Multi tasking will be more robust. Kernel will auto balance load. It should help with more free RAM after hours usage and help with more smoothness
-optimized scrolling(Beta stage)
-Optimized 2D/3D for lag free game(beta stage)
-KSM (Kernel Samepage Merging) support. It will use low RAM though will provide more performance through merging duplicate and/or inactive pages in same page more info http://en.m.wikipedia.org/wiki/Kernel_SamePage_Merging_(KSM)
-ARM sched powersaving featured
-Various optimized flags aimed for balance between stability-performance and battery management
-other changelogs is same of tb10

Downloads:
http://db.tt/faeCneQE

Sent from my LG-P990 using Tapatalk
 
Last edited:
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SuperSkill

SuperSkill

Senior Member
Jun 25, 2011
2,305
1,155
Kristiansand
I'm pleased to testbuilds coming out in good rates now, no more thanks left today, will test latest after work, but 10.zip was good, only thing ønsker, a bit high consumption during use :) keep it up :D
 
SuperSkill

SuperSkill

Senior Member
Jun 25, 2011
2,305
1,155
Kristiansand
Spica :D
If you want you can put my link to your work at first post to make it easier for all to find them :) If any of you have the few I'm missing please share or pm ;)

Thanks:)
 
TrymHansen

TrymHansen

Senior Member
Jun 7, 2011
1,108
952
spica1234 said:
Strange i have not that issue of locked 300 mhz min frequency. are you sure there is nothing left in init.d i mean no previous script which sets frequecy as per screen events on/off?
Click to expand...
Click to collapse
Yes. It's not an "issue", it's like that with all stock kernels. Minimum frequency when plugged in is 300867Hz. Look at included screenshots. Note I'm not saying anythings wrong, just stating a fact.
SR3 or SR3R2? SR3 is tool old and it was removed due to such issue with OTF.
YEs may be SR3 had that issue of 300mhz min frequency locked up which was resolved in SR3R.
Click to expand...
Click to collapse
Again, no. Min freq when plugged in is 300Mhz.
mincpu1 on : during upscaling at what min frequency it should activate 2nd core eg. 216->1015 upscaling suppost at 800mhz
maxcpu1off: during downscaling at what max frequency it will turn off 2nd core eg. 1015-> 216 downscaling suppost 503mhz
It wont take quick effect like gueste kernel. as his activation time is 200 ms while mine 2000ms(which is default set b y nvidia)
So my kernel for example will wait for 2000ms after cpu pass mincpu1on frequency after 2000ms still max ramping frequency is 800 then only it activates. suppost if after 2000ms cpu frequency has fall down then it wont activate. same for maxcpu1off

Please find SR3R version latest stable build from below link. thanks to superskill for uploading

http://xdaforums.com/showpost.php?p=24926178&postcount=4623
Click to expand...
Click to collapse
EDIT: Forget about it, it doesn't really matter, as long as it works.
 
Last edited:
V

vpaulve

Senior Member
Sep 26, 2010
239
14
spica1234 said:
Testbuild11: (OC)

-Scheduler tracing support. When launching new process. Scheduler trace cfs rq load. And decide priority for new process. Multi tasking will be more robust. Kernel will auto balance load. It should help with more free RAM after hours usage and help with more smoothness
-optimized scrolling(Beta stage)
-Optimized 2D/3D for lag free game(beta stage)
-KSM (Kernel Samepage Merging) support. It will use low RAM though will provide more performance through merging duplicate and/or inactive pages in same page more info http://en.m.wikipedia.org/wiki/Kernel_SamePage_Merging_(KSM)
-ARM sched powersaving featured
-Various optimized flags aimed for balance between stability-performance and battery management
-other changelogs is same of tb10

Downloads:
http://db.tt/faeCneQE

Sent from my LG-P990 using Tapatalk
Click to expand...
Click to collapse

Spica, this file is same than linked yesterday, 06:53 PM (10.zip), is it right? No Testbuild11?
 
spica1234

spica1234

Retired Recognized Developer
Aug 1, 2010
3,081
3,362
India
TrymHansen said:
Yes. It's not an "issue", it's like that with all stock kernels. Minimum frequency when plugged in is 300867Hz. Look at included screenshots. Note I'm not saying anythings wrong, just stating a fact.
Again, no. Min freq when plugged in is 300Mhz.
EDIT: Forget about it, it doesn't really matter, as long as it works.
Click to expand...
Click to collapse
Thank you for reporting.
Ok now i got it first i misunderstood. When plugin means during charge?

Sent from my LG-P990 using Tapatalk
 
Ferrum Master

Ferrum Master

Senior Member
Dec 22, 2010
1,117
277
Rīga
V11 broken, doesn't see external sd card anymore, freaked out at start, thought that this is a return of spica sdformatter kernel, but no... in recovery everything is fine... :p

Sent from my LG-P990 using XDA
 
spica1234

spica1234

Retired Recognized Developer
Aug 1, 2010
3,081
3,362
India
Ferrum Master said:
Just got a random reboot while charging... Just noticed the phone flashing and media scan running. Something went wrong.
Click to expand...
Click to collapse

Does it get resolved?





Ferrum Master said:
V11 broken, doesn't see external sd card anymore, freaked out at start, thought that this is a return of spica sdformatter kernel, but no... in recovery everything is fine... :p

Sent from my LG-P990 using XDA
Click to expand...
Click to collapse



Sent from my LG-P990 using Tapatalk
 
Ferrum Master

Ferrum Master

Senior Member
Dec 22, 2010
1,117
277
Rīga
No it didn't something went wrong very badly and corrupted something although vold.fstab file was normal. Cache/Dalvik wipe didn't help. Did a nandroid back... to Gueste 1.6.1... :p

So till later... maybe someone will catch something also.
 
Stefan Gündhör

Stefan Gündhör

Senior Member
Oct 24, 2011
2,368
5,748
Hinterholz 8
spica1234 said:
mincpu1 on : during upscaling at what min frequency it should activate 2nd core eg. 216->1015 upscaling suppost at 800mhz
maxcpu1off: during downscaling at what max frequency it will turn off 2nd core eg. 1015-> 216 downscaling suppost 503mhz
Click to expand...
Click to collapse


I dunno if it still matters, but you got that the wrong way round, even NVidia did in the source documentation.

maxcpu1off is the max freq second core will be off up to, after frequency is higher than this limit, second core will be turned on after being higher for longer than on-time milliseconds

mincpu1on is the frequency down to which second core should stay enabled, after freq goes lower than this boundary for longer than off-time milliseconds second core will be turned off

Have you never wondered, why NVidia asserts after setting that mincpu1on is lower than maxcpu1off? Because u turn second core on at higher freqs and off after being lower for some time again. The other ways round it wouldn't make sense and also in my kernel I use the freqs as just described and it works, as can be tested with guesteOC tool-
 
Last edited:
spica1234

spica1234

Retired Recognized Developer
Aug 1, 2010
3,081
3,362
India
Stefan Gündhör said:
I dunno if it still matters, but you got that the wrong way round, even NVidia did in the source documentation.

maxcpu1off is the max freq second core will be off up to, after frequency is higher than this limit, second core will be turned on after being higher for longer than on-time milliseconds

mincpu1on is the frequency down to which second core should stay enabled, after freq goes lower than this boundary for longer than off-time milliseconds

Have you never wondered, why NVidia asserts after setting that mincpu1on is lower than maxcpu1off? Because u turn second core on at higher freqs and off after being lower for some time again. The other ways round it wouldn't make sense and also in my kernel I use the freqs as just described and it works, as can be tested with guesteOC tool-
Click to expand...
Click to collapse
Dont take it in wrong way but,
You are wrong here bro. Mincpu1on is at which mincpufreq 2nd core will be activated.
If i set 1.2 ghz at 1ghz of max clock. It never activates 2nd core in hp 2x kernel tweaker. And if i check by system tunner it never activates 2nd core. Same way if i lowwer polling interval to 100ms for on and 200ms for off and if i set mincpu1on at 216 & off at 1.2 as of 1ghz max freq it doesnt off 2nd core. Its completely logic and working fine. Thats why my users have never issue of 2nd core remaining always on:)
Nv_assert is idealized assert. What it should be. Perfectly right when mincpu1on frequency goes above (suppose 800) there is a need for activation of 2nd core and when maxcpu1off (suppose 850) means load is off turn the second core off:)
Have you never wondered why mincpu1on is less then max cpu1 off. Neither nvidia is wrong nor me. But it makes sense.

I believed the same logic which is followed by faux123(another recognized developer maintaining 6 devices), morfic, vadonka, vork kernel(another recognized developer), pastime1971,hackworks, harsh, heil1125 and nvidia. I dont think excluding me, their logic is also wrong:)
I have done a ton of R & D in this OTF creation during my testing phaze especially with mincpu1on and maxcpu1off. That wasnt overkill but for more understanding and more robust values for OTF HP eXtended Project:) and because of those overkill testing only OTF is now super stable.
Never mind:) you believe your understanding while i believe mine. But your logic is wrong here. Chills;)

Sent from my LG-P990 using Tapatalk
 
Last edited:
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Stefan Gündhör

Stefan Gündhör

Senior Member
Oct 24, 2011
2,368
5,748
Hinterholz 8
spica1234 said:
Thats why my users have never issue of 2nd core remaining always on:)
Click to expand...
Click to collapse

Oh this issue has different reason, it didn't exist before v1.6.1 ;)
Trym and I have done much testing too, believe me. And we could exactly watch second core behavior thx to Trym's tool.
I don't say the logic of all the devs is wrong, I just say Nvidia documentation is wrong there and everyone just took the contents of the doku there for given.
Remove the NV_ASSERT line and try it again. (maybe the failing of the NV_ASSERT just completely cancels the second core turing on/off procedure)
Or best wait for Trym's tool to be out for your kernel then you can really monitor second core behavior.

By the way, NV_ASSERT asserts that mincpu1on is lower than maxcpu1off
spica1234 said:
Perfectly right when mincpu1on frequency goes above (suppose 800) there is a need for activation of 2nd core and when maxcpu1off (suppose 850) means load is off turn the second core off
Click to expand...
Click to collapse
In your logic mincpu1on is the frequency second core is turned on (when higher than this) and maxcpu1off the frequency second core is turned off (when lower than this).
Let's just assume this is true - what happens p.ex. if mincpu1on is 800 and maxcpu1off is 1000 and you run (and lock) the kernel at 900 MHz? Constant activation and deactivation of second core? :)
 
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    spica1234
    spica1234
    WARNING:THIS METHOD CAN BE DANGEROUS. DONT DO ANYTHING IF YOU DO NOT KNOW WHAT YOU DO.I AM NOT RESPONSIBLE IF YOU TRANSFORM YOUR PHONE INTO A BRICK.​

    Horse Power 2x eXtreme SuperSonic SR4R​

    Welcome to HP Development, If you like my work, you can buy me a beer:)

    I dont work for donations but they do help and helped in the past to counter accidential expenses that comming unplanned. And helped me to buy caffeine for my development.

    Here are the list of Donators who have donated so far. I'd like to thank everybody including users of HP Kernels for support, without support and contribution it cant reach till here:

    Names of Donators who donated since development of HP Kernels:

    -SuperSkill (multi time donator, greatest contributors of development)
    -Striatrum_bdr (My neuro protective donator:p)
    -yann73(Multi Time Donators)
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    -DARIO FRANZONI,
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    -sorry if i've forgot anybody's name please remind me if i've


    HP Pro SuperSonic SR4

    Changelogs(Kernel Specific)

    -too long list of changelogs
    -Included all changes since SS1 to SS21
    -HP Pro RT Scheduler removed temporarily for stability issue
    -Compiled with HP Pro SuperSonic ToolChain for maxium Performance, snappiness and fluidity

    Compiled with HP Pro SuperSonic ToolChain.​

    HP Pro SuperSonic ToolChain Features: (Based on GCC Linaro Sources)[/U][/B]

    (-) Tegra specific optimization
    (-) Toolchain Target flags has been optimized in same manner as the kernel drivers are written
    (-) "Optimizing as the way program is written". I have overy observed all the codes by , as they're written and used same appropriate optimizations
    (-) By observing codes 1st thing that comes in mind is Structures & Unions. Used Target Optimizations for it: '-fpack-struct and mstructure-size-boundary=32' for proper alignments of Structures and Unions for faster access
    (-) fivopts for variable strength optimizations
    (-) fforce-mem with fomit-frame-pointer for faster pointer access
    (-) Except tegra codes most of the kernel codes have inlined functions. All functions inlined for faster access of codes. By inlining functions it can be accessed as fast as macro
    (-) Code assembly and linking with ArmV7-A architecture's Cortex-A9 cpu's Virtulizations, Integer Division Float and Multi-Processing CPU Extensions
    (-) CortexA9 Processor has support for Array Prefetching same like windows does SW based Prefetch. This CPU features during runtime loads longer arrays in advance in CPU memory via AX/BX registers. Which can significantly improve runtime execution and overall snappiness. Target toolchain optimized with array-prefetch optimizations to compile codes with array pre-fetch instructions
    (-) By observing Tegra and LG drivers, there are very few short loops, which needs no optimizations, thus graphite loop optimizations disabled.
    (-) LTO( Link Time Optimizations) for removal of unused codes during linking stage and re-sections of functions and data for faster access
    (-) As armv7-a architecture supports Unaligned Access, instead of disabling, its optimized with 8K access
    (-) This is the same toolchain that has been used since 5 months to speedup SuperSonic Test builds for Stock Kernel. No extra blind optimizations used for issue of stability but only as drivers and kernel codes are written "Target specific optimizations" for maxium possible performance
    (-) toolchain: Complete set of Used CFLAGS_FOR_TARGET: -O0 -finline-functions -fpack-struct=8 -mstructure-size-boundary=32 -fpreferch-loop-arrays -fivopts -fforce-mem -fomit-frame-pointer CFLAGS_FOR_BUILD: -O0 -march=atom -mtune=atom( as my cpu is atom) Cflags:-O0 -finline-functions


    Download


    OC Version: https://www.dropbox.com/s/1byhged9oqw5a6n/HP_Pro_SuperSonic_SR4R_OC.zip

    No-OC Version: https://www.dropbox.com/s/uvnq7fppcsd8z7e/HP_Pro_SuperSonic_SR4R_No-OC.zip

    BIG THANKS TO SUPERSKILL & SHREEPRAJAY FOR PROVIDING ALL HP KERNEL MIRRORS WORKING LINK, IF ANYBODY ELSE HAS ALSO MIRRORED PLEASE PM ME THE LINKS:)

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    An APP To Control On-The-Fly features of RC12, A Big Thanks to Developer Keshav0001, Who without saying Created an application and still progressing, He is New to XDA as needed 10 or more posts:

    Downloads:

    search in Market "HorsePower 2x OTF Kernel Tweaker"



    Horse Power 2x eXtreme 16/24/32BPP RC12-R(RC Release)​

    This kernel is based on LG V20Q sources. This kernel is competible and should only be flashed with STOCK MCR FROYO and GINGERBREAD. NOT COMPETIBLE WITH CM AND MIUI

    Cryptic Changelogs History:

    PHP:
    Code: 
    +Fixed core cpu memory leak
+ Fixed group scheduler"s cpu memory leak, no need to restart phone every 100 hours.
+[B][U](SR3R2)[/U][/B] Reverted to original BackLight drivers as request of many users [B][U](SR3R2)[/U][/B]
+[B][U](SR3R2)[/U][/B] Fixed missing codes in PowerSave [B][U](SR3R2)[/U][/B]
+[B][U](SR3R2)[/U][/B] Fixed with NoOC Version without compcache [B][U](SR3R2)[/U][/B]
+[B][U](SR3R)[/U][/B] Fixed missing definition of CPU memory leak. After hours by hours, days by days more smoothness w/o slow down due to memory leak [B][U](SR3R)[/U][/B]
+[B][U](SR3R)[/U][/B] Full SMP support, enhancing Real Time Dual Core Performance for Multi-Tasking And activated PowerSave profile 4,5,6 [B][U](SR3R)[/U][/B]
+[B][U](SR3R)[/U][/B] Full IP Tables supported, by an upgraded IP Tables [B][U](SR3R)[/U][/B]
+[B][U](SR3R)[/U][/B] Included farajep's backlight driver (Thanks to farajep for making source available) [B][U](SR3R)[/U][/B]
+[B][U](SR3R)[/U][/B] Quick responsiveness and smoothness like SR3 [B][U](SR3R)[/U][/B]
+[B][U](SR3R)[/U][/B] Longest battery performance [B][U](SR3R)[/U][/B]
+[B][U](SR3R)[/U][/B] Fixed freeze, no need to apply +mV patch. One version for all devices [B][U](SR3R)[/U][/B]
+[B][U](SR3R)[/U][/B] Fast WiFi browsing [B][U](SR3R)[/U][/B]
+[B][U](SR3R)[/U][/B] More smooth scrolling [B][U](SR3R)[/U][/B]
+[B][U](SR3)[/U][/B] Introducing OTF V2.0 including Strong Vibrator OTF Function and many bug fixes. To activate strong vibrater just set value "1" in /data/spica/strong_vibe and save, Instantly strong vibrator driver will be activated. To enable boot time Strong Vibrator support set value "1" to /data/spicabootcfg/strong_vibe. For +mV versions and BPP patch InstallKernel first than apply patches for that  reffer post #2 after this [B][U](SR3)[/U][/B]
+[B][U](SR3)[/U][/B] Fixed EndCall BSOD(Thanks to Vadonka) [B][U](SR3)[/U][/B]
+[B][U](SR3)[/U][/B] Extra responsiveness with Low Latency Realtime Processing [B][U](SR3)[/U][/B]
+[B][U](SR3)[/U][/B] Mega Smooth UI performance and Rock Solid Stability [B][U](SR3)[/U][/B]
+[B][U](SR3)[/U][/B] Longest battery life. 2 versions available one with my modded battery driver and another with DS battery driver(jumpy-funky reading but long battery life) (Thanks to DS available sources) [B][U](SR3)[/U][/B]
+[B][U](RC12-R)[/U][/B] Longest battrery performance on v20q source kernel with RevisedOTF PowerSave functionality [B][U](RC12-R)[/U][/B]
+[B][U](RC12-R)[/U][/B] Mega Smooth UI Smoothness, You'll really be amazed by never seen smoothness [B][U](RC12-R)[/U][/B]
+[B][U](RC12-R)[/U][/B] RockSolid Stability [B][U](RC12-R)[/U][/B]
+[B][U](RC12-R)[/U][/B] Fully Functional Spica Revised OTF Pack, Lesser freeze free re-mastered values for powersave, gentle yet effective, Selected target values for powersave to significantly reduce battery drainage, PowerSave profile 1-6 (tutorial soon to be written) [B][U](RC12-R)[/U][/B]
+[B][U](RC12-R)[/U][/B] Fixed InCall BSOD previously reported with TestBuilds [B][U](RC12-R)[/U][/B]
+[B][U](RC12-R)[/U][/B] By default screen off max freq setted to 503 Mhz as always, You can exclusively play with different values On-The-Fly with RevisedOTF Functionalities for music listenings w/o distortion or for incoming call as per your needs by setting MaxScreenOff CPU freq values of choice by GUI Application (Thanks to Kaunshik001) or by writing values to /data/spica/maxscreenofffreq. No need to reply on pre-set values. [B][U](RC12-R)[/U][/B]
+[B][U](RC12)[/U][/B] On-the-fly Pack, Exported many HW controlled values from static to dynamic at userspace level (Originally I was inspired by the the concept of Xmister)([B]Credits to Xmister[/B])[B][U](RC12)[/U][/B] 
+[B][U](RC12)[/U][/B] On-the-fly VDEFREQ/GPUFREQ/MINCPU1ON/MAXCPU1OFF/SUSPEND_CORE_MV/POWERSAVE/NITROS/SCREENOFFMAXFREQ/DDR2_MIN_KHZ/LPDDR2_MIN_KHZ Support. No need to reboot/restart daemon. It works on kernel syscalls. It takes effect in notime.[B][U](RC12)[/U][/B]
+[B][U](RC12)[/U][/B] On-the-fly [B]VDEFREQ [/B]change support. Responsible file is located in /data/spica/vdefreq & /proc/spica/vdefreq. You can change the value in any of these both files. I preffer user-friendly /data/spica/vdefreq. Edit values with ES file explorer and just save file. No need to change permissions. It takes effect instantly. Default value is 600000. Supported Values in between 600000-700000. Any values above 600000 will OC it w/o increasing supplying voltage. For safety concern no values except in range will be accepted. To enable boot-time support select values in /data/spicabootcfg/vdefreq [B][U](RC12)[/U][/B]
+[B][U](RC12)[/U][/B] On-the-fly [B]GPUFREQ[/B] change support. Responsible file is located in /data/spica/gpufreq & /proc/spica/gpufreq. You can change the value in any of these both files. I preffer user-friendly /data/spica/gpufreq. Edit values with ES file explorer and just save file. No need to change permissions. It takes effect instantly. Default value is 280000. Default value is 300000 Supported Values in between 280000-350000. Any values above 280000 will OC it w/o increasing supplying voltage. For safety concern no values except in range will be accepted.To enable boot-time support select values in /data/spicabootcfg/gpufreq [B][U](RC12)[/U][/B]
+[B][U](RC12)[/U][/B] On-the-fly [B]MINCPU1ON[/B] freq change support. Means during upword scaling at what freq 2nd core will be activated. Responsible file is located in /data/spica/mincpu1on & /proc/spica/mincpu1on. You can change the value in any of these both files. I preffer user-friendly /data/spica/mincpu1on. Edit values with ES file explorer and just save file. No need to change permissions. It takes effect instantly. Default value is what you see after boot. Supported Values in between 216000-1100000. Default value of spica kernel is 810000 For safety concern no values except in range will be accepted.To enable boot-time support select values in /data/spicabootcfg/mincpu1on [B][U](RC12)[/U][/B]
+[B][U](RC12)[/U][/B] On-the-fly [B]MAXCPU1OFF[/B] freq change support. Means at what max freq 2nd core will be off during returning phaze. Responsible file is located in /data/spica/maxcpu1off & /proc/spica/maxcpu1off. You can change the value in any of these both files. I preffer user-friendly /data/spica/maxcpu1off. Edit values with ES file explorer and just save file. No need to change permissions. It takes effect instantly. Default value is what you see after boot. Supported Values in between 216000-1100000. Default value of spica kernel is 860000 For safety concern no values except in range will be accepted.To enable boot-time support select values in /data/spicabootcfg/maxpu1off [B][U](RC12)[/U][/B]
+[B][U](RC12)[/U][/B] On-the-fly [B]MaxScreenOffFreq[/B] support. Means During screen off what will be the max freq.Responsible file is located in /data/spica/screenoff_maxcpufreq & /proc/spica/screenoff_maxcpufreq. You can change the value in any of these both files. I preffer user-friendly /data/spica/maxcpu1off. Edit values with ES file explorer and just save file. No need to change permissions. It takes effect instantly. Default value is what you see after boot. Supported Values in between 216000-999000. For safety concern no values except in range will be accepted.To enable boot-time support select values in /data/spicabootcfg/screenoff_maxcpufreq. [B][U](RC12)[/U][/B]
+[B][U](RC12)[/U][/B] On-the-fly [B]DDR2 MINIMUM FREQUENCY[/B] support. It's theminimum frequency of DDR2(SDRAM).Responsible file is located in /data/spica/ddr2_min_khz & /proc/spica/ddr2_min_khz. You can change the value in any of these both files. I preffer user-friendly /data/spica/ddr2_min_khz. Edit values with ES file explorer and just save file. No need to change permissions. It takes effect instantly. Default value is what you see after boot. Supported Values in between 10000-50000. Default value is 50000 For safety concern no values except in range will be accepted.To enable boot-time support select values in /data/spicabootcfg/ddr2_min_khz. [B][U](RC12)[/U][/B]
+[B][U](RC12)[/U][/B] On-the-fly[B] LPDDR2 MINIMUM FREQUENCY[/B] support. It's theminimum frequency of LPDDR2.Responsible file is located in /data/spica/lpddr2_min_khz & /proc/spica/lpddr2_min_khz. You can change the value in any of these both files. I preffer user-friendly /data/spica/lpddr2_min_khz. Edit values with ES file explorer and just save file. No need to change permissions. It takes effect instantly. Default value is what you see after boot. Supported Values in between 1000-18000. Default value is 18000 For safety concern no values except in range will be accepted.To enable boot-time support select values in /data/spicabootcfg/lpddr2_min_khz. [B][U](RC12)[/U][/B]
+[B][U](RC12)[/U][/B] On-the-fly [B]SUSPENDED CORE VOLTAGE SUPPLY[/B] support. It's theminimum frequency of CORE VOLTAGE WHEN Core is in suspend state.Responsible file is located in /data/spica/suspend_core_mv & /proc/spica/suspend_core_mv. You can change the value in any of these both files. I preffer user-friendly /data/spica/suspend_core_mv. Edit values with ES file explorer and just save file. No need to change permissions. It takes effect instantly. Default value is what you see after boot. Supported Values in between 600-1000. Default value is 1000 For safety concern no values except in range will be accepted.To enable boot-time support select values in /data/spicabootcfg /suspend_core_mv. [B][U](RC12)[/U][/B]
+[B][U](RC12)[/U][/B] Dynamic On-The-Fly '[B]powersave'[/B] profile. Which accepts value from '0' to '6'. During 'powersave' kernel smartly adjust various thresholds of voltage to lower possible values. "0' value means disable(Defult) "1" light powersave "2" moderate powersave "3" aggressive powersave "4" Profile "1" during screen off "5" Profile "2" during only screen off "6" Profile "3" during screen off only(POWERSAVE doesnt touch UV). Make sure 'nitros' mode disable aka value '0' Responsible file location /data/spica/powersave and boot time file location /data/spicabootcfg/powersave [B][U](RC12)[/U][/B]
+[B][U](RC12)[/U][/B] Dynamic On-The-Fly "[B]Nitros[/B]" -"Performance" mode. It accepts two values, "0" Disable "1"Enable. During "Nitros" Profile Kernel sets max fail-safe values (It doesnt touch OC). File location /data/spica/nitors and boot time file location /data/spicabootcfg.Make sure 'powersave' is disabled aka value '0'[B][U](RC12)[/U][/B]
+[B][U](RC12)[/U][/B] V20Q Sources merged[B][U](RC12)[/U][/B]
+[B][U](RC12)[/U][/B] Slight loud crystal clear volume in headphone[B][U](RC12)[/U][/B]
+[B][U](RC12)[/U][/B] Optimized SCHED_RR & SCHED_FIFO[B][U](RC12)[/U][/B]
+[B][U](RC11-R)[/U][/B] Fixed CpuFreq of  2nd Core not syncing with 1st core's cpufreq. NOW Very quicker 2nd core activation and very quicker 2nd core suspension. Thus  fastest realtime resposnses and excellent reduced battery drainage. Standby battery drainage with OC/UV ~1-2mA [B][U](RC11-R)[/U][/B]
+[B][U](RC11-R)[/U][/B] Re-injected Compcache and removed ZRAM [B][U](RC11-R)[/U][/B]
+[B][U](RC11-R)[/U][/B] Modified Deadline Scheduler's FIFO parametrs to 20 instead of 16 for quicker response [B][U](RC-11R)[/U][/B]
+[B][U](RC11)[/U][/B] More snapier, stable and performance oriented [B][U](RC11)[/U][/B]
+[B][U](RC11)[/U][/B] Featuring ZRAM/(Previously known as CompCache) HW Compressed RAM with SWAP_FREE_NOTIFY feature [B][U](RC11)[/U][/B]
+[B][U](RC11)[/U][/B] Fixed freeze issue by re-compiling GCC HardFolat ARM tool chain [B][U](RC11)[/U][/B]
+[B][U](RC11)[/U][/B] OC/UV & VOODOO remerged [B][U](RC11)[/U][/B]
+[B][U](RC10)[/U][/B]Removed LG's lowmemorykiller.c and added same modified by me for assured oom optimal functionality with no possible memory leak[B][U](RC10)[/U][/B]
+[B][U](RC10)[/U][/B]Longest battery performance among all HP KRNLS. Extended battery life[B][U](RC10)[/U][/B]
+[B][U](RC10)[/U][/B]NVMAP enabled to kill processes envoked by GPU to assure GPU mem functionality without allocation of static GPU memory[B][U](RC10)[/U][/B]
+[B][U](RC10)[/U][/B]Enabled Android pMem functionality[B][U](RC10)[/U][/B]
+[B][U](RC10)[/U][/B]Patched tegra framebuffer to allow pseudo color palate support on same x,y axis with >/= 16 bits support[B][U](RC10)[/U][/B]
+[B][U](RC10)[/U][/B]Quicker apps response[B][U](RC10)[/U][/B]
+[B][U](RC10)[/U][/B]Extended most efficious multi-tasking[B][U](RC10)[/U][/B]
+[B][U](RC10)[/U][/B]ARM Hard Float VFP support. Compilation along with ARMHF tool chains[B][U](RC10)[/U][/B]
+[B][U](RC9)[/U][/B] Fully based on Official released V20L sources, Merged all HP kernel changes since beta to RC8  with V20L[B][U](RC9)[/U][/B]
+[B][U](RC9)[/U][/B]More optimized scheduling, Quicker APP response and More smooth UI (Taken from SR3 Test release)[B][U](RC9)[/U][/B]
+[B][U](RC9)[/U][/B]Fixed wifi with dynamic msallocation (Taken from SR3 Test build)[B][U](RC9)[/U][/B]
+[B][U](RC9)[/U][/B]More optimized for power saving (Taken from SR3 Test build)[B][U](RC9)[/U][/B]
+[B][U](RC9)[/U][/B]SMBFS file system support as a module (Taken from SR3 Test build) [B][U](RC9)[/U][/B]
+[B][U](SR2)[/U][/B] Power Saving optimizations [B][U](SR2)[/U][/B]
+[B][U](SR2)[/U][/B] More optimized for smoother responce [B][U](SR2)[/U][/B]
+[B][U](SR2)[/U][/B] Merged changes of RC7 & RC8 without JRCU daemon[B][U](SR2)[/U][/B]
+[B](RC8-Revised)[/B] Fixed EMC core UV issue and Max OCed reverted back to 1408Mhz[B][U](RC8-Revised)[/U][/B]
+[B][U](RC8)[/U][/B] JRCU as daemon support[B][U](RC8)[/U][/B]
+[B][U](RC8)[/U][/B] OCed upto 1.55 Ghz Normal Vibrator Version[B][U](RC8)[/U][/B]
+[B][U](RC8)[/U][/B] More possible optimizations for lesser battery drainage[B][U](RC8)[/U][/B]
+[B][U](RC7)[/U][/B] Watchdog Support added: Tegra ODM Watchdog support as a module[B][U](RC7)[/U][/B]
+[B][U](RC7)[/U][/B] SDRAM related EMC core voltage undervolted to -50mV[B][U](RC7)[/U][/B]
+[B][U](RC7)[/U][/B] More possibly optimized for better possible battery[B][U](RC7)[/U][/B]
+[B][U](RC7)[/U][/B] Max OC frequency back to 1.4Ghz[B][U](RC7)[/U][/B]
+[B][U](SR1)[/U][/B] Strong Vibrator driver, Both version availibility with Strong Vibrator driver and with Default vibrator driver [B][U](SR1)[/U][/B]
+[B][U](SR1)[/U][/B] Best hand-picked stuff from RCs, Default frequencies of CPU towards 1.4Ghz[B][U](SR1)[/U][/B]
+[B][U](SR1)[/U][/B] Assured Stability, Better Performance and energy-saving battery performance[B][U](SR1)[/U][/B]
+[B][U](RC6)[/U][/B] TEMP info fixed[B][U](RC6)[/U][/B]
+[B][U](RC6)[/U][/B]Minor debug clean-ups[B][U](RC6)[/U][/B]
+[B][U](RC6)[/U][/B] In-call volume mute issue in Froyo fixed[B][U](RC6)[/U][/B]
+[B][U](RC5)[/U][/B] OCed upto 1.5Ghz, New freq steps 216,389,655,816,1015,1216,1408,1504[B][U](RC5)[/U][/B]
+[B][U](RC5)[/U][/B] Declaration of NVODM FULL VOLTAGE in mV undefined ,Depends now on FUSE functionality .Low and Critical NVODM voltage in mV selected 9400 & 8800 respectively in NVODM initialization file[B][U](RC5)[/U][/B]
+[B][U](RC5)[/U][/B] All Kernel drivers from SU660 GB sources except power,odm_kit,base,nvos fixed for the competibility and merged[B][U](RC5)[/U][/B]
+[B][U](RC5)[/U][/B] "Anticipatory" I/O scheduler as mainline scheduler[B][U](RC5)[/U][/B]
+[B][U](RC5)[/U][/B] Compiled with GCC-4.6.2 Linaro tool chain with Voku's favourite -Ofast flags. Removed tegra specific flags and added ARM standard graphic optimized flags for cortex-a9. CFLAGS_KERNEL and MODFLAGS: -Ofast -pipe -mcpu=cortex-a9 -mtune=cortex-a9 -mfpu=vfpv3-d16 -mfloat-abi=soft -floop-block -floop-interchange -floop-strip-mine -ffast-math -funsafe-loop-optimizations -funsafe-math-optimizations -fbranch-target-load-optimize2[B][U](RC5)[/U][/B]
+[B][U](RC4)[/U][/B] Dual SPI drivers supporting HSPA+ from su660[B][U](RC4)[/U][/B]
+[B][U](RC4)[/U][/B] Wifi modules fixed for re-loading issue and Quicker connect after several hours (Needs testing)[B][U](RC4)[/U][/B]
+[B][U](RC4)[/U][/B] Regluator & RTC drivers from SU660[B][U](RC4)[/U][/B]
+[B][U](RC4)[/U][/B] Battery driver reverted to modified RC1 driver[B][U](RC4)[/U][/B]
+[B][U](RC3)[/U][/B] Featuring BPP(Bits-Per-Pixel) On-The-Fly Support, select bits in init.d/bpp file and reboot[B][U](RC3)[/U][/B]
+[B][U](RC3)[/U][/B] Modified star_battery_charger.c to allow extra-voltage charge [B][U](RC3)[/U][/B]
+[B][U](RC3)[/U][/B] Some drivers previously merged from SU660 reverted as of no visible improvement , And new NVOS NVDDK CORE drivers merged from SU660[B][U](RC3)[/U][/B]
+[B][U](RC3)[/U][/B]SCHED_FIFO optimizations for quicker SCHED operations [B][U](RC3)[/U][/B]
+[B][U](RC3)[/U][/B]Voodoo and missing batt temp in RC2 fixed with RC3[B][U](RC3)[/U][/B]
+[B][U](RC3) [/U][/B] More optimized SCHED_OTHER & SCHED_RR/FIFO for optimum I/O operation[B][U](RC3)[/U][/B]
+[B][U](RC 2)[/U][/B]NEW released su660's V20D GB kernel sources' WLAN module, MMC, USB, I2C, MTD, SPI, NVRM, NVODM, ODM_KIT, STAR, POWER dirvers fixed for the competibility and merged[B][U](RC 2)[/U][/B]
+[B][U](RC 2)[/U][/B]Ext2 support enabled.[B][U](RC 2)[/U][/B]
+[B][U](RC1)[/U][/B] Fixed pre-mature reboots on Terminal Emulator, USB debugging, Script Manager, Compeitble with Andrev OC Daemon APP, fixed reboot on restart daemon service.[B][U](RC1)[/U][/B]
+[B][U](RC1)[/U][/B] Optimized for Quicker APPs response[B][U](RC1)[/U][/B]
+[B][U](RC1)[/U][/B] 32BPP/24BPP Tegra-FB enabled kernel. For 32BPP, Enabled Virtual A8R8G8B8 32BPP to 24BPP to 18BPP panle color with changed RGB and Transperency OFFSET and LENGTH[B][U](RC1)[/U][/B]
+[B][U](RC1)[/U][/B] Heridant topogigi's vold.fstab in installation zip file, for preventing unmounted SD issue on other ROMs [B][U](RC1)[/U][/B]
+[B][U](RC1)[/U][/B] tocuhscreen fix credits to pastime[B][U](RC1)[/U][/B]
+[B](Beta1.1)[/B] Re-strctured modded battery driver with Beta1. OverHeat suspenstion now supports 410-550 TEMP instead of 450-550. Assured up-to 50% lesser battery drainage. Battery driver now supports scaling through 3360 to 4182 mv instead of 4150mv[B].(Beta1.1)[/B]
+Mega-smooth UI Fluidity/smoothness and higher benchmarks
+Quicker UI and/or APP responsiveness
+Efficient multi-tasking
+OC/UV Codes merged from Cpsjuste Sources([B]Thanks cpsjuste ,impertius sources available[/B])
+Voodoo codes from [B]Supecorio[/B] sources(Thanks)
+Ext4 supported
+Competible with V20 l/j/g/i/c/e/q/p/o/l/m And Froyo MCR



    If you appreciate my work than feel free to Support My O2x Development



    Recommendation:
    -Battery calibration. After calibration let it disachrge full for the first time then full charge. Then you're ready to go! Full discharge needs to be done ONLY ONCE after calibration.
    Procedure:
    -charge phone full when its off, start phone. Charge till it shows full status. Charge more for 15mins untill you see battery voltage at 4182mv. Then calibrate battery with Battery Calibration App.
    HP TB Sources: https://github.com/spica234/HP-TestBuild-Repo-upwords-Sr3R
    HP 2x Kernel Sources since RC1 to Sr3R2: https://github.com/spica234/HP-2X-V20Q
    HP 2x Deprecated Sources since RC1 to RC11 https://github.com/spica234/HP-Krnl-2.6.32.9
    revOTF Patch Attached in the post!
    View
    23
    spica1234
    spica1234
    Got an hour of time today.

    Finished writing HP Pro RT(Real Time) Scheduler and now remained to restore my backup and to merge changes into kernel. And to check for testing for stability as I/O RT processing changes are known for system instabilities.
    Users interested to test can PM me so as soon as I could get time to restore my OS to build kernel

    Info about HP Pro RT(Real Time) Schedular Load Balancing For Any Kernel For Any Devices:

    {*} periodicallyscanning running processes and auto prioritizing of processes for new processes for adequate load balancing for the max Real Time responsiveness
    {*} To be merged with OOM and android low memory killer to make low memory killer easier
    {*} unrelating with cpu prioritizing and making stand alone max Input/Output throughput
    {°} Many more still pending. Limiting factor for me is time:/

    Main aim set to be achieved:
    Max responsiveness during Multi-Tasking and performance related to snappiness by intellectualy prioritizing dynamic runtime resource management as per load requirement and to limit cpu and io as and when needed as per actual load for max battery

    Q: Why it was needed(for me)?
    A: Because only optimizing cpu management isnt crucial as performance depends on I/O resourses management aswell

    Edit:
    More implementation to be done in OTFV3.0:
    + memory leak to be fixed present in OTFv2
    +DCA (Direct Cache(L1 &L2) Access) for OTF V3.0
    +Continueous Memory Alignment for OTFV3 for faster OTF module loading and unloading and for faster OTF access
    +To be fixxed unaligned 64K access caused by memcpy() in OTFV2
    +to implement 8K Unaligned Direct Memory Access for OTFV3.0


    Sent from my LG-P990 using Tapatalk 2
    View
    22
    spica1234
    spica1234
    HP Pro SuperSonic12 TestBuild:

    HP Pro SuperSonic12 Embeded TestBuild:

    Changelogs:

    +As always alike other SuperSonic series compiled with HP Pro SuperSonic Toolchain
    +More ARM Multi-Threading improvements for the best performance. And better Parallel Multi-Tasking
    + ARM isb mode Level 1(L1) & Level 2(L2) 32 bit cpu-cache acess with 50% L1 to L2 reserved response with Full 50% cache-flushing for better smoothness & more responsiveness. CPU L1 and L2 Cache is the more specific area this build is optimized for.
    +Various memory leaks fixed, now always free ram near about ~200MB anytime. No micro-lag even after hours.
    +Faster Application loading and processing, Faster gallery loading
    +Visibly Optimized 2D/3D. Visible improvements in FPS in games and various benchmarks. 2D FPS Atleast +5 FPS and 3D atleast +5-6 FPS
    +Using extensive ARM Powermanagement
    +Structures same as previous built re-mapped in 32 bit boundaries.
    +Ferrum bug fixed.
    +Various hysteresis values change for stability
    +I guess this is the smoothest and fastest build in SuperSonic Series.
    +Major Break-Through Performance Oriented Supersonic series release

    Download:

    http://db.tt/5Ky6uldU
    View
    20
    spica1234
    spica1234
    Thanks to all HP users

    Alright guys, This is a Final Build for a while, as I'm starting ICS kernel development, But I dont want this GB kernel development to be abandoned, Because It's really deep hard work of mine. And it's the journey I begin with here on XDA. So I'll always update it once in every 10-15 day and whenever LG releases new kernel sources to give you maxium the Best Of Me:) I must Thank every HP users who joined journey since Beta to SR3R. If I've not recieved such a good appreciation then I might have not come so far, Thanks to everybody:)

    I do hold a good job, But after being married, it is hard to afford many expensises which comes after daily expense. One of them is HDD primary failure. I'm still using my Data Traveller(mini HD) as a main HD which was provided to me by my company I work for:). Although I've save almost half amount(some by my job salary and some by donators who donated to me, thanking them) for buying new HDD. I dont even like to ask for but I hope you can understand, If I've not lost my HDD then I even might have put no DONATE button either like the past days:)

    So if anybody who wishes to support my serious dedication and My O2X Development can DONATE to me now . DONATE link:) It will help me buy a new HDD sooner to continue my Further Development at full force:)

    And great thanks to every Donators who has donated so far:) Thanks to SuperSkill, Striatrum_bdr, wapz, Basil 123, Steieve, yan73, civato, carburano, psonic2k, PhunKee, zerocoolrider (Sorry If i have forgotten anybody's name, Please remind me)
    View
    15
    spica1234
    spica1234
    GentlyCriminal said:
    Everybody is showing him the deepest respect and is thankful, he's work is amazing, but i'm refreshing this thread probably every 30min, because he told us he will upload it yesterday, so i don't think it is unrespectful when somebody asks for uploading. This waiting is just killing you.
    Click to expand...
    Click to collapse

    Sorry yesterday it was ready fully stable and responsive but with inCall BSOD . If i remove my OTF then no BSOD And fully stable i could either name it SR3. But i want to launch RC12-R without OTFcause that's my very much hardwork with proven benefits and w/o adding nothing new i dont wanna increment SR and RC series by nothing new but same old with recompile with whatever worked. Cause wrting new codes for new implements is not enough atleast for platform OS for mobile where every phone has different story with different reactions so need a lot testing. I am really sorry for giving commitment for release, from now on words I wont commit nor mention anything untill next version is fully ready. Once again Sorry for the commit of release I made. I returned home from job now and working single hand for BSOD fix for my OTF. It could take a minute or hours to get it solved. Thank you once again for the patience and Sorry once again for the wrong estd commit I gave:)

    Sent from my LG-P990 using Tapatalk
    View

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