Hi All
I recently bricked my Acer A210 and it's running in APX mode. In a effort to bring it back to life i have been researching the jtag setup.
As you can see from this image, on the rigth hand side is JDBUG1, with pin 1 mark at the top.
Now this is a A510 in the image, but the same 10 pin connect is on my A210 and possibly on the A700,
Now using many different tegra3 manuals and dev board guides i've reversed the jtag connector, well mostly, I've some more to confirm but i though i would put this out there in case any one has any thing to add, i will also upload as much info as i have and the pdf in case any one want to confirm my research,
Hopefully we can fix without $$$$ hardware.
I have a o'scope (30 years old crt based) ,arduino, buspirate, Open Source logic sniffer.
The latter two from dangerous prototypes, the main one i will use is the bus pirate in jtag mode.
I have already connected the buspirate up but no results i could rely on so i went back to research, here is what i've turned up ,
Now this information has been gleamed from many sources.
please see attached images for now, on the A210 the tracks are more exposed but I think its safe to assum the debug connector pin outs would be the same for the 3 devices,
EDIT** Ive found the A510 Schematic Online A510 Schematic - See Page 7 for JTAG
darkspr1te
I recently bricked my Acer A210 and it's running in APX mode. In a effort to bring it back to life i have been researching the jtag setup.
As you can see from this image, on the rigth hand side is JDBUG1, with pin 1 mark at the top.
Now this is a A510 in the image, but the same 10 pin connect is on my A210 and possibly on the A700,
Now using many different tegra3 manuals and dev board guides i've reversed the jtag connector, well mostly, I've some more to confirm but i though i would put this out there in case any one has any thing to add, i will also upload as much info as i have and the pdf in case any one want to confirm my research,
Hopefully we can fix without $$$$ hardware.
I have a o'scope (30 years old crt based) ,arduino, buspirate, Open Source logic sniffer.
The latter two from dangerous prototypes, the main one i will use is the bus pirate in jtag mode.
I have already connected the buspirate up but no results i could rely on so i went back to research, here is what i've turned up ,
Code:
1 1.8v Tegra System Voltage
2 TRST (on A210 a 0R resistor is missing or 'un-stuffed' or not 'stuffed', see info about tying to gnd for CPU access )
3 10K to +v 1.8v for TDI
4 10K to +v 1.8v for TMS
5 100K to GND for TCK
6 10K to GND for RTCK (Return clock , see [URL="http://en.wikipedia.org/wiki/Joint_Test_Action_Group"]RTCK wiki[/URL] )
7 TDO (direct into CPU )
8 HOT_RESET (1.8v)
9 ON_KEY# (+5v )
10 GND
Now this information has been gleamed from many sources.
please see attached images for now, on the A210 the tracks are more exposed but I think its safe to assum the debug connector pin outs would be the same for the 3 devices,
EDIT** Ive found the A510 Schematic Online A510 Schematic - See Page 7 for JTAG
darkspr1te
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