so i start to find the way how to unbrick it without nvflash wheelie Secure Boot Key (blob.bin) because i not backup it. and still i don't know how to backup it!?
After a long research tegra based schematics and nvidia tegra dev docs, some forum posts, for my prime i got the idea from google nexus 7 schematic there used same pin con. figure
this post nexus7 sch http://forum.xda-developers.com/show...0&postcount=86
i find in printed circuit board GMI_OE_N, FORCE_RECOVERY#, and Uart Debug, jtag. connector pinout for comminication but that socket and some resistor used only for development process and test. its unmounted for production.
first i try FORCE_RECOVERY# pin when i power on tablet short it with ground device entered directly APX mode but that is same with vol power button combination tegra Soc still not allowed me to access emmc nand.
I started to research uart debugin i find this post http://forum.xda-developers.com/show....php?t=1081743 little information about howto tegra uart debug to understand what has happened to the bootloader
in experiment first i see in terminal garbage ascii characters i change TTL the location of the wire uart TXD, and uart RXD. "UART_DEBUG_TXD <-> UART_DEBUG_RXD" for tf201 showed me the right uart log in terminal meybe jtag pins are different placed i still not sure? but F_Recovery, pin and Hot_reset, pin are in same place VDD1.8v pin where have in right placed! i have edit schematic picture with paint for correction
i use for Uart debugin Usb TTL adapter pl2303 and PuTTY terminal emulator
How to: UART
1. Connect TTL to source device TX
2. Connect TTL RxD to source device RX
3. Connect TTL GND to source device GND! (don't forgot it!)
5. Open a terminal emulator, like PuTTY.
115200, 8 n 1, no flow control
Warning! Use this information at your own risk. Will void your warranty!
!don't Unmount nothing in pcb!
edited by me 24pin con. points schematic
mb pad connector pic
here is the power on boot debug log
-Mé11AÁé¢ÂZ¡é)9YI8 -MéAUéºZ¡é)9YI8I8 1= ½¹ÑÉ½±±ÉéªRre%Õiêjjj¥*áÑÉ¹ ½¹ÑÉ½±±ÉéªRş ADJUSTED CLOCKS: MC clock is set to 250000 KHz EMC clock is set to 500000 KHz (DDR clock is at 500000 KHz) PLLX0 clock is set to 700000 KHz PLLC0 clock is set to 600000 KHz CPU clock is set to 700000 KHz System and AVP clock is set to 102000 KHz GraphicsHost clock is set to 163200 KHz 3D clock is set to 83333 KHz 2D clock is set to 83333 KHz Epp clock is set to 83333 KHz Mpe clock is set to 83333 KHz Vde clock is set to 272000 KHz Bootloader Start at:2017 ms PCB value(0x0) Initializing Display PCB value(0x0) PCB value(0x0) PCB value(0x0) PCB value(0x0) Inval idate-only cache maint not supported in NvOs PCB value(0x0) PCB value(0x0) PCB value(0x0) PCB value(0x0) PCB value(0x0) PCB value(0x0) LowLowBatteryCheck LowLowBattery Check pinvalue=0 Battery capacity >low low Battery voltage PCB value(0x0)Show mdpilogo show logo at 2814ms [bootloader] (built on Nov 22 2012, 20:19:53) Platform Pre Boot configuration... Verify chip uid chip uid 1st RSAVerify ok The Device is UnLocked. SocCpuMaxKHz = 1000000 SocCpuMinKHz = 32 PLLX0 FreqKHz = 700000 Checking for android ota recovery PCB value(0x0) Platform Pre OS Boot configuration... HDMI CPLD Program - ERROR HDMI CPLD Program - ERROR CpldRead8(): Failed: SlaveNotFound slave Add 0xd2 The enabling SDMMC1 Power rail is FAILED. Actual Size = 0x540800 bytes Verify chip uid chip uid 1st RSAVerify ok The proc BoardInfo: 0x0222:0x8200:0xe0:0x4f:0x44 PCB value(0x0) !!!ERROR!!! EKS Partition is not available Jumping to kernel at:3737 ms "END"
i find jelly bean internal FLASH ROM partition table documentation for lg x4 HD tegra3 based SoC
The EKS hidden partition 2M
The "NVEKSP" logo, followed by a 2048-bit key and guess verify boot.img with the public key. Using RAS (guess) algorithm SOS and LNX partition data do signature verification, signature data block (1024 bytes) in the tail of the SOS and LNX partition data.