WARNING:THIS METHOD CAN BE DANGEROUS. DONT DO ANYTHING IF YOU DO NOT KNOW WHAT YOU DO.I AM NOT RESPONSIBLE IF YOU TRANSFORM YOUR PHONE INTO A BRICK.
Horse Power 2x eXtreme SuperSonic SR4R
Welcome to HP Development, If you like my work, you can buy me a beer
I dont work for donations but they do help and helped in the past to counter accidential expenses that comming unplanned. And helped me to buy caffeine for my development.
Here are the list of Donators who have donated so far. I'd like to thank everybody including users of HP Kernels for support, without support and contribution it cant reach till here:
Names of Donators who donated since development of HP Kernels:
-SuperSkill (multi time donator, greatest contributors of development)
-Striatrum_bdr (My neuro protective donator
)-yann73(Multi Time Donators)
-Carburano( Thanks my friend)
-Civato(Thanks my friend)
-wapz
-Basil 123
-Steieve
-psonic2k
-PhunKee
-zerocoolrider
-fuxman
-skylight
-shreeprajay
-patiiet
-Omar Cornejo Sanchez
-abwyatt,-
-tablighs
-Rehborn-
-Jonas Andrulis
-Chris Daßler
- Bert van Hoesel
-Miguel Angel Mulero Martinez
-DARIO FRANZONI,
-Antonello Picerno
-sorry if i've forgot anybody's name please remind me if i've
HP Pro SuperSonic SR4
Changelogs(Kernel Specific)
-too long list of changelogs
-Included all changes since SS1 to SS21
-HP Pro RT Scheduler removed temporarily for stability issue
-Compiled with HP Pro SuperSonic ToolChain for maxium Performance, snappiness and fluidity
Compiled with HP Pro SuperSonic ToolChain.
HP Pro SuperSonic ToolChain Features: (Based on GCC Linaro Sources)[/U][/B]
(-) Tegra specific optimization
(-) Toolchain Target flags has been optimized in same manner as the kernel drivers are written
(-) "Optimizing as the way program is written". I have overy observed all the codes by , as they're written and used same appropriate optimizations
(-) By observing codes 1st thing that comes in mind is Structures & Unions. Used Target Optimizations for it: '-fpack-struct and mstructure-size-boundary=32' for proper alignments of Structures and Unions for faster access
(-) fivopts for variable strength optimizations
(-) fforce-mem with fomit-frame-pointer for faster pointer access
(-) Except tegra codes most of the kernel codes have inlined functions. All functions inlined for faster access of codes. By inlining functions it can be accessed as fast as macro
(-) Code assembly and linking with ArmV7-A architecture's Cortex-A9 cpu's Virtulizations, Integer Division Float and Multi-Processing CPU Extensions
(-) CortexA9 Processor has support for Array Prefetching same like windows does SW based Prefetch. This CPU features during runtime loads longer arrays in advance in CPU memory via AX/BX registers. Which can significantly improve runtime execution and overall snappiness. Target toolchain optimized with array-prefetch optimizations to compile codes with array pre-fetch instructions
(-) By observing Tegra and LG drivers, there are very few short loops, which needs no optimizations, thus graphite loop optimizations disabled.
(-) LTO( Link Time Optimizations) for removal of unused codes during linking stage and re-sections of functions and data for faster access
(-) As armv7-a architecture supports Unaligned Access, instead of disabling, its optimized with 8K access
(-) This is the same toolchain that has been used since 5 months to speedup SuperSonic Test builds for Stock Kernel. No extra blind optimizations used for issue of stability but only as drivers and kernel codes are written "Target specific optimizations" for maxium possible performance
(-) toolchain: Complete set of Used CFLAGS_FOR_TARGET: -O0 -finline-functions -fpack-struct=8 -mstructure-size-boundary=32 -fpreferch-loop-arrays -fivopts -fforce-mem -fomit-frame-pointer CFLAGS_FOR_BUILD: -O0 -march=atom -mtune=atom( as my cpu is atom) Cflags:-O0 -finline-functions
Download
OC Version: https://www.dropbox.com/s/1byhged9oqw5a6n/HP_Pro_SuperSonic_SR4R_OC.zip
No-OC Version: https://www.dropbox.com/s/uvnq7fppcsd8z7e/HP_Pro_SuperSonic_SR4R_No-OC.zip
BIG THANKS TO SUPERSKILL & SHREEPRAJAY FOR PROVIDING ALL HP KERNEL MIRRORS WORKING LINK, IF ANYBODY ELSE HAS ALSO MIRRORED PLEASE PM ME THE LINKS
Downlaod HP Krnls(Latest Build is SR3R2/R:
https://www.box.com/s/5995c4bdcf9abb4e375f
Download HP Performance Packs
https://www.box.com/s/d2a5c32bd3cc0e5d174f
An APP To Control On-The-Fly features of RC12, A Big Thanks to Developer Keshav0001, Who without saying Created an application and still progressing, He is New to XDA as needed 10 or more posts:
Downloads:
search in Market "HorsePower 2x OTF Kernel Tweaker"
Horse Power 2x eXtreme 16/24/32BPP RC12-R(RC Release)
This kernel is based on LG V20Q sources. This kernel is competible and should only be flashed with STOCK MCR FROYO and GINGERBREAD. NOT COMPETIBLE WITH CM AND MIUI
Cryptic Changelogs History:
PHP:
Code:
+Fixed core cpu memory leak
+ Fixed group scheduler"s cpu memory leak, no need to restart phone every 100 hours.
+[B][U](SR3R2)[/U][/B] Reverted to original BackLight drivers as request of many users [B][U](SR3R2)[/U][/B]
+[B][U](SR3R2)[/U][/B] Fixed missing codes in PowerSave [B][U](SR3R2)[/U][/B]
+[B][U](SR3R2)[/U][/B] Fixed with NoOC Version without compcache [B][U](SR3R2)[/U][/B]
+[B][U](SR3R)[/U][/B] Fixed missing definition of CPU memory leak. After hours by hours, days by days more smoothness w/o slow down due to memory leak [B][U](SR3R)[/U][/B]
+[B][U](SR3R)[/U][/B] Full SMP support, enhancing Real Time Dual Core Performance for Multi-Tasking And activated PowerSave profile 4,5,6 [B][U](SR3R)[/U][/B]
+[B][U](SR3R)[/U][/B] Full IP Tables supported, by an upgraded IP Tables [B][U](SR3R)[/U][/B]
+[B][U](SR3R)[/U][/B] Included farajep's backlight driver (Thanks to farajep for making source available) [B][U](SR3R)[/U][/B]
+[B][U](SR3R)[/U][/B] Quick responsiveness and smoothness like SR3 [B][U](SR3R)[/U][/B]
+[B][U](SR3R)[/U][/B] Longest battery performance [B][U](SR3R)[/U][/B]
+[B][U](SR3R)[/U][/B] Fixed freeze, no need to apply +mV patch. One version for all devices [B][U](SR3R)[/U][/B]
+[B][U](SR3R)[/U][/B] Fast WiFi browsing [B][U](SR3R)[/U][/B]
+[B][U](SR3R)[/U][/B] More smooth scrolling [B][U](SR3R)[/U][/B]
+[B][U](SR3)[/U][/B] Introducing OTF V2.0 including Strong Vibrator OTF Function and many bug fixes. To activate strong vibrater just set value "1" in /data/spica/strong_vibe and save, Instantly strong vibrator driver will be activated. To enable boot time Strong Vibrator support set value "1" to /data/spicabootcfg/strong_vibe. For +mV versions and BPP patch InstallKernel first than apply patches for that reffer post #2 after this [B][U](SR3)[/U][/B]
+[B][U](SR3)[/U][/B] Fixed EndCall BSOD(Thanks to Vadonka) [B][U](SR3)[/U][/B]
+[B][U](SR3)[/U][/B] Extra responsiveness with Low Latency Realtime Processing [B][U](SR3)[/U][/B]
+[B][U](SR3)[/U][/B] Mega Smooth UI performance and Rock Solid Stability [B][U](SR3)[/U][/B]
+[B][U](SR3)[/U][/B] Longest battery life. 2 versions available one with my modded battery driver and another with DS battery driver(jumpy-funky reading but long battery life) (Thanks to DS available sources) [B][U](SR3)[/U][/B]
+[B][U](RC12-R)[/U][/B] Longest battrery performance on v20q source kernel with RevisedOTF PowerSave functionality [B][U](RC12-R)[/U][/B]
+[B][U](RC12-R)[/U][/B] Mega Smooth UI Smoothness, You'll really be amazed by never seen smoothness [B][U](RC12-R)[/U][/B]
+[B][U](RC12-R)[/U][/B] RockSolid Stability [B][U](RC12-R)[/U][/B]
+[B][U](RC12-R)[/U][/B] Fully Functional Spica Revised OTF Pack, Lesser freeze free re-mastered values for powersave, gentle yet effective, Selected target values for powersave to significantly reduce battery drainage, PowerSave profile 1-6 (tutorial soon to be written) [B][U](RC12-R)[/U][/B]
+[B][U](RC12-R)[/U][/B] Fixed InCall BSOD previously reported with TestBuilds [B][U](RC12-R)[/U][/B]
+[B][U](RC12-R)[/U][/B] By default screen off max freq setted to 503 Mhz as always, You can exclusively play with different values On-The-Fly with RevisedOTF Functionalities for music listenings w/o distortion or for incoming call as per your needs by setting MaxScreenOff CPU freq values of choice by GUI Application (Thanks to Kaunshik001) or by writing values to /data/spica/maxscreenofffreq. No need to reply on pre-set values. [B][U](RC12-R)[/U][/B]
+[B][U](RC12)[/U][/B] On-the-fly Pack, Exported many HW controlled values from static to dynamic at userspace level (Originally I was inspired by the the concept of Xmister)([B]Credits to Xmister[/B])[B][U](RC12)[/U][/B]
+[B][U](RC12)[/U][/B] On-the-fly VDEFREQ/GPUFREQ/MINCPU1ON/MAXCPU1OFF/SUSPEND_CORE_MV/POWERSAVE/NITROS/SCREENOFFMAXFREQ/DDR2_MIN_KHZ/LPDDR2_MIN_KHZ Support. No need to reboot/restart daemon. It works on kernel syscalls. It takes effect in notime.[B][U](RC12)[/U][/B]
+[B][U](RC12)[/U][/B] On-the-fly [B]VDEFREQ [/B]change support. Responsible file is located in /data/spica/vdefreq & /proc/spica/vdefreq. You can change the value in any of these both files. I preffer user-friendly /data/spica/vdefreq. Edit values with ES file explorer and just save file. No need to change permissions. It takes effect instantly. Default value is 600000. Supported Values in between 600000-700000. Any values above 600000 will OC it w/o increasing supplying voltage. For safety concern no values except in range will be accepted. To enable boot-time support select values in /data/spicabootcfg/vdefreq [B][U](RC12)[/U][/B]
+[B][U](RC12)[/U][/B] On-the-fly [B]GPUFREQ[/B] change support. Responsible file is located in /data/spica/gpufreq & /proc/spica/gpufreq. You can change the value in any of these both files. I preffer user-friendly /data/spica/gpufreq. Edit values with ES file explorer and just save file. No need to change permissions. It takes effect instantly. Default value is 280000. Default value is 300000 Supported Values in between 280000-350000. Any values above 280000 will OC it w/o increasing supplying voltage. For safety concern no values except in range will be accepted.To enable boot-time support select values in /data/spicabootcfg/gpufreq [B][U](RC12)[/U][/B]
+[B][U](RC12)[/U][/B] On-the-fly [B]MINCPU1ON[/B] freq change support. Means during upword scaling at what freq 2nd core will be activated. Responsible file is located in /data/spica/mincpu1on & /proc/spica/mincpu1on. You can change the value in any of these both files. I preffer user-friendly /data/spica/mincpu1on. Edit values with ES file explorer and just save file. No need to change permissions. It takes effect instantly. Default value is what you see after boot. Supported Values in between 216000-1100000. Default value of spica kernel is 810000 For safety concern no values except in range will be accepted.To enable boot-time support select values in /data/spicabootcfg/mincpu1on [B][U](RC12)[/U][/B]
+[B][U](RC12)[/U][/B] On-the-fly [B]MAXCPU1OFF[/B] freq change support. Means at what max freq 2nd core will be off during returning phaze. Responsible file is located in /data/spica/maxcpu1off & /proc/spica/maxcpu1off. You can change the value in any of these both files. I preffer user-friendly /data/spica/maxcpu1off. Edit values with ES file explorer and just save file. No need to change permissions. It takes effect instantly. Default value is what you see after boot. Supported Values in between 216000-1100000. Default value of spica kernel is 860000 For safety concern no values except in range will be accepted.To enable boot-time support select values in /data/spicabootcfg/maxpu1off [B][U](RC12)[/U][/B]
+[B][U](RC12)[/U][/B] On-the-fly [B]MaxScreenOffFreq[/B] support. Means During screen off what will be the max freq.Responsible file is located in /data/spica/screenoff_maxcpufreq & /proc/spica/screenoff_maxcpufreq. You can change the value in any of these both files. I preffer user-friendly /data/spica/maxcpu1off. Edit values with ES file explorer and just save file. No need to change permissions. It takes effect instantly. Default value is what you see after boot. Supported Values in between 216000-999000. For safety concern no values except in range will be accepted.To enable boot-time support select values in /data/spicabootcfg/screenoff_maxcpufreq. [B][U](RC12)[/U][/B]
+[B][U](RC12)[/U][/B] On-the-fly [B]DDR2 MINIMUM FREQUENCY[/B] support. It's theminimum frequency of DDR2(SDRAM).Responsible file is located in /data/spica/ddr2_min_khz & /proc/spica/ddr2_min_khz. You can change the value in any of these both files. I preffer user-friendly /data/spica/ddr2_min_khz. Edit values with ES file explorer and just save file. No need to change permissions. It takes effect instantly. Default value is what you see after boot. Supported Values in between 10000-50000. Default value is 50000 For safety concern no values except in range will be accepted.To enable boot-time support select values in /data/spicabootcfg/ddr2_min_khz. [B][U](RC12)[/U][/B]
+[B][U](RC12)[/U][/B] On-the-fly[B] LPDDR2 MINIMUM FREQUENCY[/B] support. It's theminimum frequency of LPDDR2.Responsible file is located in /data/spica/lpddr2_min_khz & /proc/spica/lpddr2_min_khz. You can change the value in any of these both files. I preffer user-friendly /data/spica/lpddr2_min_khz. Edit values with ES file explorer and just save file. No need to change permissions. It takes effect instantly. Default value is what you see after boot. Supported Values in between 1000-18000. Default value is 18000 For safety concern no values except in range will be accepted.To enable boot-time support select values in /data/spicabootcfg/lpddr2_min_khz. [B][U](RC12)[/U][/B]
+[B][U](RC12)[/U][/B] On-the-fly [B]SUSPENDED CORE VOLTAGE SUPPLY[/B] support. It's theminimum frequency of CORE VOLTAGE WHEN Core is in suspend state.Responsible file is located in /data/spica/suspend_core_mv & /proc/spica/suspend_core_mv. You can change the value in any of these both files. I preffer user-friendly /data/spica/suspend_core_mv. Edit values with ES file explorer and just save file. No need to change permissions. It takes effect instantly. Default value is what you see after boot. Supported Values in between 600-1000. Default value is 1000 For safety concern no values except in range will be accepted.To enable boot-time support select values in /data/spicabootcfg /suspend_core_mv. [B][U](RC12)[/U][/B]
+[B][U](RC12)[/U][/B] Dynamic On-The-Fly '[B]powersave'[/B] profile. Which accepts value from '0' to '6'. During 'powersave' kernel smartly adjust various thresholds of voltage to lower possible values. "0' value means disable(Defult) "1" light powersave "2" moderate powersave "3" aggressive powersave "4" Profile "1" during screen off "5" Profile "2" during only screen off "6" Profile "3" during screen off only(POWERSAVE doesnt touch UV). Make sure 'nitros' mode disable aka value '0' Responsible file location /data/spica/powersave and boot time file location /data/spicabootcfg/powersave [B][U](RC12)[/U][/B]
+[B][U](RC12)[/U][/B] Dynamic On-The-Fly "[B]Nitros[/B]" -"Performance" mode. It accepts two values, "0" Disable "1"Enable. During "Nitros" Profile Kernel sets max fail-safe values (It doesnt touch OC). File location /data/spica/nitors and boot time file location /data/spicabootcfg.Make sure 'powersave' is disabled aka value '0'[B][U](RC12)[/U][/B]
+[B][U](RC12)[/U][/B] V20Q Sources merged[B][U](RC12)[/U][/B]
+[B][U](RC12)[/U][/B] Slight loud crystal clear volume in headphone[B][U](RC12)[/U][/B]
+[B][U](RC12)[/U][/B] Optimized SCHED_RR & SCHED_FIFO[B][U](RC12)[/U][/B]
+[B][U](RC11-R)[/U][/B] Fixed CpuFreq of 2nd Core not syncing with 1st core's cpufreq. NOW Very quicker 2nd core activation and very quicker 2nd core suspension. Thus fastest realtime resposnses and excellent reduced battery drainage. Standby battery drainage with OC/UV ~1-2mA [B][U](RC11-R)[/U][/B]
+[B][U](RC11-R)[/U][/B] Re-injected Compcache and removed ZRAM [B][U](RC11-R)[/U][/B]
+[B][U](RC11-R)[/U][/B] Modified Deadline Scheduler's FIFO parametrs to 20 instead of 16 for quicker response [B][U](RC-11R)[/U][/B]
+[B][U](RC11)[/U][/B] More snapier, stable and performance oriented [B][U](RC11)[/U][/B]
+[B][U](RC11)[/U][/B] Featuring ZRAM/(Previously known as CompCache) HW Compressed RAM with SWAP_FREE_NOTIFY feature [B][U](RC11)[/U][/B]
+[B][U](RC11)[/U][/B] Fixed freeze issue by re-compiling GCC HardFolat ARM tool chain [B][U](RC11)[/U][/B]
+[B][U](RC11)[/U][/B] OC/UV & VOODOO remerged [B][U](RC11)[/U][/B]
+[B][U](RC10)[/U][/B]Removed LG's lowmemorykiller.c and added same modified by me for assured oom optimal functionality with no possible memory leak[B][U](RC10)[/U][/B]
+[B][U](RC10)[/U][/B]Longest battery performance among all HP KRNLS. Extended battery life[B][U](RC10)[/U][/B]
+[B][U](RC10)[/U][/B]NVMAP enabled to kill processes envoked by GPU to assure GPU mem functionality without allocation of static GPU memory[B][U](RC10)[/U][/B]
+[B][U](RC10)[/U][/B]Enabled Android pMem functionality[B][U](RC10)[/U][/B]
+[B][U](RC10)[/U][/B]Patched tegra framebuffer to allow pseudo color palate support on same x,y axis with >/= 16 bits support[B][U](RC10)[/U][/B]
+[B][U](RC10)[/U][/B]Quicker apps response[B][U](RC10)[/U][/B]
+[B][U](RC10)[/U][/B]Extended most efficious multi-tasking[B][U](RC10)[/U][/B]
+[B][U](RC10)[/U][/B]ARM Hard Float VFP support. Compilation along with ARMHF tool chains[B][U](RC10)[/U][/B]
+[B][U](RC9)[/U][/B] Fully based on Official released V20L sources, Merged all HP kernel changes since beta to RC8 with V20L[B][U](RC9)[/U][/B]
+[B][U](RC9)[/U][/B]More optimized scheduling, Quicker APP response and More smooth UI (Taken from SR3 Test release)[B][U](RC9)[/U][/B]
+[B][U](RC9)[/U][/B]Fixed wifi with dynamic msallocation (Taken from SR3 Test build)[B][U](RC9)[/U][/B]
+[B][U](RC9)[/U][/B]More optimized for power saving (Taken from SR3 Test build)[B][U](RC9)[/U][/B]
+[B][U](RC9)[/U][/B]SMBFS file system support as a module (Taken from SR3 Test build) [B][U](RC9)[/U][/B]
+[B][U](SR2)[/U][/B] Power Saving optimizations [B][U](SR2)[/U][/B]
+[B][U](SR2)[/U][/B] More optimized for smoother responce [B][U](SR2)[/U][/B]
+[B][U](SR2)[/U][/B] Merged changes of RC7 & RC8 without JRCU daemon[B][U](SR2)[/U][/B]
+[B](RC8-Revised)[/B] Fixed EMC core UV issue and Max OCed reverted back to 1408Mhz[B][U](RC8-Revised)[/U][/B]
+[B][U](RC8)[/U][/B] JRCU as daemon support[B][U](RC8)[/U][/B]
+[B][U](RC8)[/U][/B] OCed upto 1.55 Ghz Normal Vibrator Version[B][U](RC8)[/U][/B]
+[B][U](RC8)[/U][/B] More possible optimizations for lesser battery drainage[B][U](RC8)[/U][/B]
+[B][U](RC7)[/U][/B] Watchdog Support added: Tegra ODM Watchdog support as a module[B][U](RC7)[/U][/B]
+[B][U](RC7)[/U][/B] SDRAM related EMC core voltage undervolted to -50mV[B][U](RC7)[/U][/B]
+[B][U](RC7)[/U][/B] More possibly optimized for better possible battery[B][U](RC7)[/U][/B]
+[B][U](RC7)[/U][/B] Max OC frequency back to 1.4Ghz[B][U](RC7)[/U][/B]
+[B][U](SR1)[/U][/B] Strong Vibrator driver, Both version availibility with Strong Vibrator driver and with Default vibrator driver [B][U](SR1)[/U][/B]
+[B][U](SR1)[/U][/B] Best hand-picked stuff from RCs, Default frequencies of CPU towards 1.4Ghz[B][U](SR1)[/U][/B]
+[B][U](SR1)[/U][/B] Assured Stability, Better Performance and energy-saving battery performance[B][U](SR1)[/U][/B]
+[B][U](RC6)[/U][/B] TEMP info fixed[B][U](RC6)[/U][/B]
+[B][U](RC6)[/U][/B]Minor debug clean-ups[B][U](RC6)[/U][/B]
+[B][U](RC6)[/U][/B] In-call volume mute issue in Froyo fixed[B][U](RC6)[/U][/B]
+[B][U](RC5)[/U][/B] OCed upto 1.5Ghz, New freq steps 216,389,655,816,1015,1216,1408,1504[B][U](RC5)[/U][/B]
+[B][U](RC5)[/U][/B] Declaration of NVODM FULL VOLTAGE in mV undefined ,Depends now on FUSE functionality .Low and Critical NVODM voltage in mV selected 9400 & 8800 respectively in NVODM initialization file[B][U](RC5)[/U][/B]
+[B][U](RC5)[/U][/B] All Kernel drivers from SU660 GB sources except power,odm_kit,base,nvos fixed for the competibility and merged[B][U](RC5)[/U][/B]
+[B][U](RC5)[/U][/B] "Anticipatory" I/O scheduler as mainline scheduler[B][U](RC5)[/U][/B]
+[B][U](RC5)[/U][/B] Compiled with GCC-4.6.2 Linaro tool chain with Voku's favourite -Ofast flags. Removed tegra specific flags and added ARM standard graphic optimized flags for cortex-a9. CFLAGS_KERNEL and MODFLAGS: -Ofast -pipe -mcpu=cortex-a9 -mtune=cortex-a9 -mfpu=vfpv3-d16 -mfloat-abi=soft -floop-block -floop-interchange -floop-strip-mine -ffast-math -funsafe-loop-optimizations -funsafe-math-optimizations -fbranch-target-load-optimize2[B][U](RC5)[/U][/B]
+[B][U](RC4)[/U][/B] Dual SPI drivers supporting HSPA+ from su660[B][U](RC4)[/U][/B]
+[B][U](RC4)[/U][/B] Wifi modules fixed for re-loading issue and Quicker connect after several hours (Needs testing)[B][U](RC4)[/U][/B]
+[B][U](RC4)[/U][/B] Regluator & RTC drivers from SU660[B][U](RC4)[/U][/B]
+[B][U](RC4)[/U][/B] Battery driver reverted to modified RC1 driver[B][U](RC4)[/U][/B]
+[B][U](RC3)[/U][/B] Featuring BPP(Bits-Per-Pixel) On-The-Fly Support, select bits in init.d/bpp file and reboot[B][U](RC3)[/U][/B]
+[B][U](RC3)[/U][/B] Modified star_battery_charger.c to allow extra-voltage charge [B][U](RC3)[/U][/B]
+[B][U](RC3)[/U][/B] Some drivers previously merged from SU660 reverted as of no visible improvement , And new NVOS NVDDK CORE drivers merged from SU660[B][U](RC3)[/U][/B]
+[B][U](RC3)[/U][/B]SCHED_FIFO optimizations for quicker SCHED operations [B][U](RC3)[/U][/B]
+[B][U](RC3)[/U][/B]Voodoo and missing batt temp in RC2 fixed with RC3[B][U](RC3)[/U][/B]
+[B][U](RC3) [/U][/B] More optimized SCHED_OTHER & SCHED_RR/FIFO for optimum I/O operation[B][U](RC3)[/U][/B]
+[B][U](RC 2)[/U][/B]NEW released su660's V20D GB kernel sources' WLAN module, MMC, USB, I2C, MTD, SPI, NVRM, NVODM, ODM_KIT, STAR, POWER dirvers fixed for the competibility and merged[B][U](RC 2)[/U][/B]
+[B][U](RC 2)[/U][/B]Ext2 support enabled.[B][U](RC 2)[/U][/B]
+[B][U](RC1)[/U][/B] Fixed pre-mature reboots on Terminal Emulator, USB debugging, Script Manager, Compeitble with Andrev OC Daemon APP, fixed reboot on restart daemon service.[B][U](RC1)[/U][/B]
+[B][U](RC1)[/U][/B] Optimized for Quicker APPs response[B][U](RC1)[/U][/B]
+[B][U](RC1)[/U][/B] 32BPP/24BPP Tegra-FB enabled kernel. For 32BPP, Enabled Virtual A8R8G8B8 32BPP to 24BPP to 18BPP panle color with changed RGB and Transperency OFFSET and LENGTH[B][U](RC1)[/U][/B]
+[B][U](RC1)[/U][/B] Heridant topogigi's vold.fstab in installation zip file, for preventing unmounted SD issue on other ROMs [B][U](RC1)[/U][/B]
+[B][U](RC1)[/U][/B] tocuhscreen fix credits to pastime[B][U](RC1)[/U][/B]
+[B](Beta1.1)[/B] Re-strctured modded battery driver with Beta1. OverHeat suspenstion now supports 410-550 TEMP instead of 450-550. Assured up-to 50% lesser battery drainage. Battery driver now supports scaling through 3360 to 4182 mv instead of 4150mv[B].(Beta1.1)[/B]
+Mega-smooth UI Fluidity/smoothness and higher benchmarks
+Quicker UI and/or APP responsiveness
+Efficient multi-tasking
+OC/UV Codes merged from Cpsjuste Sources([B]Thanks cpsjuste ,impertius sources available[/B])
+Voodoo codes from [B]Supecorio[/B] sources(Thanks)
+Ext4 supported
+Competible with V20 l/j/g/i/c/e/q/p/o/l/m And Froyo MCRIf you appreciate my work than feel free to Support My O2x Development
Recommendation:
-Battery calibration. After calibration let it disachrge full for the first time then full charge. Then you're ready to go! Full discharge needs to be done ONLY ONCE after calibration.
Procedure:
-charge phone full when its off, start phone. Charge till it shows full status. Charge more for 15mins untill you see battery voltage at 4182mv. Then calibrate battery with Battery Calibration App.
HP TB Sources: https://github.com/spica234/HP-TestBuild-Repo-upwords-Sr3R
HP 2x Kernel Sources since RC1 to Sr3R2: https://github.com/spica234/HP-2X-V20Q
HP 2x Deprecated Sources since RC1 to RC11 https://github.com/spica234/HP-Krnl-2.6.32.9
revOTF Patch Attached in the post!
Attachments
Last edited:
