Nexus 7 POGO GPIO PINS on Side

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peterpressure

Member
Jul 23, 2012
18
10
So similar to what was found on the Samsung Galaxy Nexus, does anyone know where the source file exists that explains what the 4 POGO pins on the left side of the Nexus 7 are for? I cannot figure them out with my multimeter or oscilloscope.

Samsung Galaxy POGO thread: http://forum.xda-developers.com/showthread.php?t=1614287
File on Samsung Galaxy Nexus was board-tuna-pogo.c but that is obviously not on the Nexus 7 because it is made by Asus and I assume they had a different file.

Nexus%207%20pogo%20pins%20on%20left%20side-580-100.jpg

Close up of the POGO insternals from ifixit.com:
ImqfPU61sZDC35Rd.medium
 

kpjimmy

Senior Member
Jan 20, 2009
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My assumption is that there will be a dock of some sort that will be using those contacts.

I make this assumption from my old Nexus One where they also had contacts similar for charging. :confused:
 

OriginalFire

Member
Jul 6, 2012
40
10
I'm not entirely sure, but one of the pins could be for charging and another for ground. And possibly the other two are for audio out.

Just a guess lol

Sent from my HTC One X using xda app-developers app
 

tomascivinod

Senior Member
Sep 2, 2009
62
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Sydney
Since there are 4 pins, I get the feeling it could be USB? 2 for data + 2 for power and since now Android has support for USB audio it wouldn't matter? I just wonder how you could do power and stereo audio since you would need a ground + 2 for audio and 2 for power...
 

khaytsus

Senior Member
Apr 8, 2008
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Since there are 4 pins, I get the feeling it could be USB? 2 for data + 2 for power and since now Android has support for USB audio it wouldn't matter? I just wonder how you could do power and stereo audio since you would need a ground + 2 for audio and 2 for power...

Nope, ground is ground. Could use the negative terminal for ground, so could be + l r -
 

rmm200

Senior Member
Apr 15, 2011
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One thing for sure, unlike the title of this topic, they are not GPIO pins.

My vote is for stereo audio, ground, and charging. Buy a dock from Asus and see.
 

peterpressure

Member
Jul 23, 2012
18
10
One thing for sure, unlike the title of this topic, they are not GPIO pins.

My vote is for stereo audio, ground, and charging. Buy a dock from Asus and see.

If Asus had one available I would buy it!

That said, here is what I found so far...

Top Pin (1): Ground
2: ???
3: ???
4: Data (minus) ???

Tried hot glueing wires into the pogo ports to conduct more tests, but quickly realized it was easier to just pop the back off and wire them directly to the board itself.

C360_2012-07-27-11-34-21.jpg

C360_2012-07-28-10-44-05.jpg

C360_2012-07-28-10-44-42.jpg

C360_2012-07-28-10-45-05.jpg

C360_2012-07-28-10-47-03.jpg

C360_2012-07-28-10-51-20.jpg

C360_2012-07-28-10-55-12.jpg

C360_2012-07-28-11-35-11.jpg
 

jb7890

New member
Jul 31, 2012
1
4
POGO connection product from ASUS

Here's the product that connects to the pins:

http://www.droid-life.com/2012/07/30/official-nexus-7-accessory-lineup-leaks-pogo-dock-incoming/

JB



So similar to what was found on the Samsung Galaxy Nexus, does anyone know where the source file exists that explains what the 4 POGO pins on the left side of the Nexus 7 are for? I cannot figure them out with my multimeter or oscilloscope.

Samsung Galaxy POGO thread: http://forum.xda-developers.com/showthread.php?t=1614287
File on Samsung Galaxy Nexus was board-tuna-pogo.c but that is obviously not on the Nexus 7 because it is made by Asus and I assume they had a different file.

Nexus%207%20pogo%20pins%20on%20left%20side-580-100.jpg

Close up of the POGO insternals from ifixit.com:
ImqfPU61sZDC35Rd.medium
 

peterpressure

Member
Jul 23, 2012
18
10
Here's the product that connects to the pins

Well, I am hellbent on beating Asus to the punch!

Protip: apply 5V between your pin 1 and 4 and watch dmesg.

Thank you for this tip! Great help.

I apply GND to pin 1 (top pin) and 5V to pin 4, dmesg (cat /proc/kmsg in Terminal Emulator) says the following upon +5volt insertion.

<4>[ 232.369780] INOK=L
<5>[ 232.370361] smb347_charger: [cable_type_detect] Reg3F : 0x03
<4>[ 232.370850] USBIN=0
<4>[ 232.371113] inok_isr_work_function -


When I remove +5volts it outputs the following:

<4>[ 241.459841] INOK=H
<4>[ 241.460260] ========================================================
<4>[ 241.460933] battery_callback usb_cable_state = 0
<4>[ 241.461296] ========================================================
<4>[ 241.461969] inok_isr_work_function -


But it never starts charging! ARGHHH!!!!
 

ryhamster

Senior Member
Jul 3, 2011
73
14
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essex
hmm im looking it my self i tryed 2 cables and i didnt work how ever i did im guna get a mutimeter cables and use the pins on that so see what it does
 

peterpressure

Member
Jul 23, 2012
18
10

clockcycle

Senior Member
Dec 28, 2007
3,664
811
Miami, FL
tinkering rox!

Anticipation! I hope you find out the details and are able to make something nice out of it.

My suggestion would be to make something small/slender, that could be adapted to any standard folio type case for the N7 which would allow it to "dock" without taking it out of the casing and use what ever features are available via the POGO.

GL!

-CC
 

mippen

Member
Apr 23, 2007
38
1
Is it possible to see if the pins is routed anywhere on PCB?
What kind of hardware (text on chip etc) can be found close to pins?

Is there any direct connection to usb from the pins?
If possible, ohm measure would be interesting.
 

pokey9000

Senior Member
Apr 17, 2007
767
396
Austin
Is it possible to see if the pins is routed anywhere on PCB?
What kind of hardware (text on chip etc) can be found close to pins?

Is there any direct connection to usb from the pins?
If possible, ohm measure would be interesting.

The two middle pins don't have any of the voltages you'd need for USB host handshake. In fact they're high impedance at DC. I'm pretty sure they're AC coupled audio out.

---------- Post added at 12:56 PM ---------- Previous post was at 12:51 PM ----------

Ok, small update!

Turn the tablet off, and apply GND to Pin 1 (top pin) and +5Volts to Pin 4 (Bottom pin) and Voila!

IT IS CHARGING via the POGO pins! (but only when turned off)

When I turn the tablet on, it stops charging.

So the dock charging is implemented in the bootloader but not in the kernel. Expect an OS update around the time the dock is released.

BTW Bluetooth V2.0+EDR Audio Communications Module... Sounds fun
 

peterpressure

Member
Jul 23, 2012
18
10
My suggestion would be to make something small/slender, that could be adapted to any standard folio type case for the N7 which would allow it to "dock" without taking it out of the casing and use what ever features are available via the POGO.

Exactly!

Is it possible to see if the pins is routed anywhere on PCB?
What kind of hardware (text on chip etc) can be found close to pins?

Is there any direct connection to usb from the pins?
If possible, ohm measure would be interesting.

So this tablet is very easy to open. I kept looking inside but it is a multilayer PCB, so without further disassembly it would be hard to see.
I think we can figure it out via other means.

The two middle pins don't have any of the voltages you'd need for USB host handshake. In fact they're high impedance at DC. I'm pretty sure they're AC coupled audio out.

How can I test this with a sound device?

So the dock charging is implemented in the bootloader but not in the kernel. Expect an OS update around the time the dock is released.

I hope this is not the case! Seems ridiculous to require the user update the OS to use the dock, but who knows.

i got the same thing on the pogo pins only if its turned off but doesnt charge for long

I charged all the way from 0% to 100% via the pogo pins today (with the tablet off). Worked like a charm for me!
 

LouZiffer

Senior Member
Mar 16, 2010
117
43
How can I test this with a sound device?

The simplest test, assuming there is no detection going on to enable those pins (they're always enabled): Take any amplifier with a set of speakers, turn its volume all the way down, and turn it off. Run a wire from one of those supposed audio pins to a right or left input on the amp. Run another wire from the output/ground on that terminal to ground. Turn the amp on. Play sound on the tablet and gradually turn the volume up.

If the sound is reproduced by the amp, they're enabled and functional. If not, the tablet may need to be fully docked and receiving power before it enables the audio pins.
 
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  • 9
    Right. Let's stop the guessing.

    I checked out the LATEST branch of the tegra android kernel, it's called android-tegra3-grouper-3.1-jb-mr1-fr at this point in time and you will have to get it from androidsource.com I think. This branch may have bugs but it also fully supports the docking functionality. Upon applying 5V to the bottom pin and ground to the top you enable "dock mode". This shows as AC charging and cuts out the speaker. This also enabled the audio pins on the side, and though I didn't use a pair of powered speakers, I used a piezo element to confirm there is output, there was. Pin 2 is the right audio channel and pin 3 is the left. In this mode if you have headphones plugged in too they will be used over the dock connector output.

    This branch also contains a "bach" and "nakasi_3g" variant, which appear to be more or less the same. The nakasi_3g variant is also called ME370TG. The bach and nakasi_3g variants appear to be identical as in the enum they are listed as the same. It would appear this kernel supports the ril fully as upon boot it attempts to initialize it, but doesn't since we have the wrong variant.

    Finally the sound driver references a UART mode though I am yet to find how to trigger it. It appears to rely on having a Nexus 7 using the TI PMIC however I don't quite see why, I think it may be to stop it enabling normally. It's commit references a "line-out" pin, I'm not quite sure what they are referring to. If anyone knows I'll be happy to hear.

    I've posted my compiled kernel at http://www.mediafire.com/?9yw1qq52ql0ns0x . It is a stock kernel other than the branch it's taken from and so it has no special modifications or optimizations. I have provided it as an initrd.img and zImage suitable for starting with fastboot boot. The initrd.img is taken straight from the latest CM10 nightly and will not work with most other ROMs. You can always take their initrd.img from their boot.img. It's to do with the class path.
    8
    NO DATA... they are for charging and audio out only. Just look at the "official" docks that are coming out soon, they have a MicroUSB charge port and an audio out. No data, no video.

    Looking at the schematics, it is interesting to see that the pogo pins were originally going to be a normal USB port - on Sheet 14 the pins for port USB3 are marked as such, then crossed out. I suspect it was a 'nice-to-have-if-we-have-time' thing, unlike many of the bits that got crossed out during Google's design review... those bits usually correspond to traces that are still actually on the boards, with pads for components that were no longer needed.

    Sheet 28 is most interesting... it shows that the middle two pins are basically the same signals sent down the ribbon cable to the speakers/headphone (HPOUTR2, HPOUTL2), with the same LINOUT_DET signal telling the Tegra that headphones or a dock with speakers are being used, so don't play through the internal speakers.

    When power is applied to DOCK_5V (pogo pin 1) it gates through to DOCK_IN#, which says (in a note) that it hooks to GPIO_PU5 on the Tegra but it really hooks to GPIO_PU4, where it is also labeled as MB_DET_DOCK#. That whole block of GPIO pins has a string of z's running past it in a note, denoting 'sleep'; the other pins include BT_EN, BT_WAKEUP, GPS_PWRON, AP_CHARGING#, and BT_IRQ#.

    The middle two pogo pins are interesting as well... in addition to stereo signals, HPOUTL2 & HPOUTR2 are connected to UART_DEBUG_(T|R)XD lines on sheets 12 and 24. Sheet 24 shows that those signals are brought to the JTAG port (makes sense, since it is right there); Sheet 12 shows that they become UART1_(T|R)XD (and, prior to Google's review, which removed the bridging resistors, UART4_(T|R)XD), which are marked as DEBUG_GPIO(0|1) with a big "Debug??" note next to them from the earlier review.

    All told it looks like the Dock was intended to be more than just a way to get power in and noise out... having the middle pins route through to the JTAG port and to diagnostic pins on the Tegra implies that they intended to use the pogo pins to get data out as well... but perhaps that is just for testing new boards or something, I don't know.

    - M
    7
    thanks, but the best would be to illustrate this along with the location of audio-R and audio-L on a picture or a schema, so it is clear for everyboby.

    Envoyé depuis mon Nexus 7

    Its been discussed in this thread already but here is a pic


    Sent from my Nexus 7 using xda premium
    6
    I have read this thread and realized that some pics of the dock internals might be appreciated.

    I am wanting to build a custom dock also, but don't want to risk frying anything.

    So I decided to buy the dock and post pics. Hopefully someone knows about the internals....

    uploadfromtaptalk1358724464821.jpguploadfromtaptalk1358724489775.jpguploadfromtaptalk1358724507843.jpguploadfromtaptalk1358724536835.jpguploadfromtaptalk1358724549159.jpguploadfromtaptalk1358724572392.jpg


    All the pictures I have are higher quality, but xda mobile won't let me attach them for some reason...
    Sent from my Nexus 4 using xda app-developers app
    5

    Please do not clutter this thread with anything other than real findings related to the software or hardware involved with the POGO pins.

    Ok, small update!

    Turn the tablet off, and apply GND to Pin 1 (top pin) and +5Volts to Pin 4 (Bottom pin) and Voila!

    IT IS CHARGING via the POGO pins! (but only when turned off)

    When I turn the tablet on, it stops charging.

    Pictures:
    C360_2012-08-01-12-31-00.jpg

    C360_2012-08-01-12-30-29.jpg