Nexus 7 POGO GPIO PINS on Side

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Charles IV

Senior Member
Jan 15, 2016
Is there any way I can just strip the cable from a cheap charger, place it at the correct place on a wooden "stand" and just lay the tablet down in the right place to charge it?
That's all I want right now, charging without having to diddle with the cable.

It probably wont work, but in theory, yes.

I've been spending the whole day holding a stripped cable against my tablet, breaking the cable, stripping it again, and holding it against my tablet.

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    Right. Let's stop the guessing.

    I checked out the LATEST branch of the tegra android kernel, it's called android-tegra3-grouper-3.1-jb-mr1-fr at this point in time and you will have to get it from I think. This branch may have bugs but it also fully supports the docking functionality. Upon applying 5V to the bottom pin and ground to the top you enable "dock mode". This shows as AC charging and cuts out the speaker. This also enabled the audio pins on the side, and though I didn't use a pair of powered speakers, I used a piezo element to confirm there is output, there was. Pin 2 is the right audio channel and pin 3 is the left. In this mode if you have headphones plugged in too they will be used over the dock connector output.

    This branch also contains a "bach" and "nakasi_3g" variant, which appear to be more or less the same. The nakasi_3g variant is also called ME370TG. The bach and nakasi_3g variants appear to be identical as in the enum they are listed as the same. It would appear this kernel supports the ril fully as upon boot it attempts to initialize it, but doesn't since we have the wrong variant.

    Finally the sound driver references a UART mode though I am yet to find how to trigger it. It appears to rely on having a Nexus 7 using the TI PMIC however I don't quite see why, I think it may be to stop it enabling normally. It's commit references a "line-out" pin, I'm not quite sure what they are referring to. If anyone knows I'll be happy to hear.

    I've posted my compiled kernel at . It is a stock kernel other than the branch it's taken from and so it has no special modifications or optimizations. I have provided it as an initrd.img and zImage suitable for starting with fastboot boot. The initrd.img is taken straight from the latest CM10 nightly and will not work with most other ROMs. You can always take their initrd.img from their boot.img. It's to do with the class path.
    NO DATA... they are for charging and audio out only. Just look at the "official" docks that are coming out soon, they have a MicroUSB charge port and an audio out. No data, no video.

    Looking at the schematics, it is interesting to see that the pogo pins were originally going to be a normal USB port - on Sheet 14 the pins for port USB3 are marked as such, then crossed out. I suspect it was a 'nice-to-have-if-we-have-time' thing, unlike many of the bits that got crossed out during Google's design review... those bits usually correspond to traces that are still actually on the boards, with pads for components that were no longer needed.

    Sheet 28 is most interesting... it shows that the middle two pins are basically the same signals sent down the ribbon cable to the speakers/headphone (HPOUTR2, HPOUTL2), with the same LINOUT_DET signal telling the Tegra that headphones or a dock with speakers are being used, so don't play through the internal speakers.

    When power is applied to DOCK_5V (pogo pin 1) it gates through to DOCK_IN#, which says (in a note) that it hooks to GPIO_PU5 on the Tegra but it really hooks to GPIO_PU4, where it is also labeled as MB_DET_DOCK#. That whole block of GPIO pins has a string of z's running past it in a note, denoting 'sleep'; the other pins include BT_EN, BT_WAKEUP, GPS_PWRON, AP_CHARGING#, and BT_IRQ#.

    The middle two pogo pins are interesting as well... in addition to stereo signals, HPOUTL2 & HPOUTR2 are connected to UART_DEBUG_(T|R)XD lines on sheets 12 and 24. Sheet 24 shows that those signals are brought to the JTAG port (makes sense, since it is right there); Sheet 12 shows that they become UART1_(T|R)XD (and, prior to Google's review, which removed the bridging resistors, UART4_(T|R)XD), which are marked as DEBUG_GPIO(0|1) with a big "Debug??" note next to them from the earlier review.

    All told it looks like the Dock was intended to be more than just a way to get power in and noise out... having the middle pins route through to the JTAG port and to diagnostic pins on the Tegra implies that they intended to use the pogo pins to get data out as well... but perhaps that is just for testing new boards or something, I don't know.

    - M
    thanks, but the best would be to illustrate this along with the location of audio-R and audio-L on a picture or a schema, so it is clear for everyboby.

    Envoyé depuis mon Nexus 7

    Its been discussed in this thread already but here is a pic

    Sent from my Nexus 7 using xda premium
    I have read this thread and realized that some pics of the dock internals might be appreciated.

    I am wanting to build a custom dock also, but don't want to risk frying anything.

    So I decided to buy the dock and post pics. Hopefully someone knows about the internals....


    All the pictures I have are higher quality, but xda mobile won't let me attach them for some reason...
    Sent from my Nexus 4 using xda app-developers app

    Please do not clutter this thread with anything other than real findings related to the software or hardware involved with the POGO pins.

    Ok, small update!

    Turn the tablet off, and apply GND to Pin 1 (top pin) and +5Volts to Pin 4 (Bottom pin) and Voila!

    IT IS CHARGING via the POGO pins! (but only when turned off)

    When I turn the tablet on, it stops charging.


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