It is shipped in increasing volumes in smartphones and tablets.
Cortex-A9 is available as a single processor solution offering an overall performance enhancement of well above 50% compared to ARM Cortex-A8 solutions.
Cortex-A9 is available with either synthesizable or hard-macro implementations.
ARM Development Suite 5 (DS-5) tools and enhanced CoreSight Debug & Trace IP like CoreSight SoC-400 and CoreSight Design Kit for Cortex-A9 (DK-A9) allow instant software development that is backed by a broad software ecosystem.
The ARM Cortex-A9 processor is a high-performance, low-power, ARM macrocell with an L1 cache subsystem that provides full virtual memory capabilities. The Cortex-A9 processor implements the ARMv7-A architecture profile and can execute 32-bit ARM instructions, 16-bit and 32-bit Thumb instructions, and 8-bit Java bytecodes in Jazelle state.
In the ARM Cortex-A9 multiprocessor configuration, up to four Cortex-A9 processors are available in a cache-coherent cluster, under the control of a Snoop Control Unit (SCU), that maintains L1 data cache coherency. SCU is also responsible for:
- Accelerator Coherency Port (ACP) coherency operations
- routing transactions on Cortex-A9 MPCore AXI master interfaces
- Cortex-A9 uniprocessor accesses to private memory regions.
The Accelerator Coherency Port (ACP) is an optional AXI 64-bit slave port that can be connected to non-cached AXI master peripherals, such as a DMAengine or cryptographic engine.
This AMBA 3 AXI compatible slave interface on the SCU provides an interconnect point for a range of system masters.
- The ARM Cortex-A9 Processors
- Wikipedia:ARM Cortex-A9 MPCore
- ARM Architecture Reference Manual ARMv7-A and ARMv7-R (A&R profile) edition
- AMBA and AXI
- MediaTek - MT6575
- http://www.mediatek.com/_en/01_products/04_pro.php?sn=1074 MediaTek - MT6577]