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Epson S1D13774

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LCD controller found in RAPH800 and BLAC100 -- perhaps others.

Registers:

enum eReg
{
    REG0000_PRODUCT_0        = 0x0000,   // Product Information Register 0 [READONLY]
    REG0004_PRODUCT_1        = 0x0004,   // Product Information Register 1 [READONLY]
    REG0008_CFG_PIN_STATUS   = 0x0008,   // Configuration Pin Status Register [READONLY]
    REG000C_MDDI_PHY_CONFIG  = 0x000C,   // MDDI PHY Configuration Register [RESERVED]
    REG0010_MDDI_PHY_POWER   = 0x0010,   // MDDI PHY Power Down Register [RESERVED]
    REG0014_MDDI_WAKE_UP     = 0x0014,   // MDDI Wake Up Trigger Enable Register
    REG0018_PIN_DRIVE_CTRL   = 0x0018,   // Pin Drive Control Register
    REG0020_PLL_0            = 0x0020,   // PLL Setting Register 0
    REG0024_PLL_1            = 0x0024,   // PLL Setting Register 1
    REG0028_CLOCK_SOURCE     = 0x0028,   // Clock Source Select Register
    REG002C_POWER_SAVE       = 0x002C,   // Power Save Mode Register
    REG0030_I2C_QUICK_ENABLE = 0x0030,   // I2C Quick Enable Register
    REG0040_SOFT_RESET       = 0x0040,   // Software Reset Register [WRITEONLY]
    REG0080_SDRAM_RESET      = 0x0080,   // Memory Controller Software Reset Register [WRITEONLY]
    REG0084_SDRAM_REFRESH    = 0x0084,   // Auto Refresh Interval Setting Register
    REG0088_SDRAM_POWER_ON   = 0x0088,   // Power On Sequence Timing Control Register
    REG008C_SDRAM_TIMING     = 0x008C,   // Timing Control Register
    REG0094_SDRAM_STATUS     = 0x0094,   // Memory Control Status Flag Register [READONLY]
    REG0100_LCD_CLOCK        = 0x0100,   // LCD Interface Clock Setting Register
    REG0104_LCD_CONFIG       = 0x0104,   // LCD Interface Configuration Register
    REG0108_LCD_COMMAND      = 0x0108,   // LCD Interface Command Register
    REG010C_LCD_PARAM        = 0x010C,   // LCD Interface Parameter Register
    REG0110_LCD_ID           = 0x0110,   // LCD Interface ID Register
    REG0114_LCD2_FRAME_XFER  = 0x0114,   // LCD2 Interface Frame Transfer Register
    REG0140_LCD1_HT          = 0x0140,   // LCD1 Horizontal Total (FPLINE Period) Register
    REG0144_LCD1_HDP         = 0x0144,   // LCD1 Horizontal Display Period Register
    REG0148_LCD1_HDPS        = 0x0148,   // LCD1 Horizontal Display Period Start Position Register
    REG014C_LCD1_HP          = 0x014C,   // LCD1 Horizontal Pulse (FPLINE) Register
    REG0150_LCD1_HPS         = 0x0150,   // LCD1 Horizontal Pulse (FPLINE) Start Position Register
    REG0154_LCD1_VT          = 0x0154,   // LCD1 Vertical Total (FPFRAME Period) Register
    REG0158_LCD1_VDP         = 0x0158,   // LCD1 Vertical Display Period Register
    REG015C_LCD1_VDPS        = 0x015C,   // LCD1 Vertical Display Period Start Position Register
    REG0160_LCD1_VP          = 0x0160,   // LCD1 Vertical Pulse (FPFRAME) Register
    REG0164_LCD1_VPS         = 0x0164,   // LCD1 Vertical Pulse (FPFRAME) Start Position Register
    REG0168_LCD1_SERIAL      = 0x0168,   // LCD1 Serial Interface Setting Register
    REG016C_LCD1_T_PANEL     = 0x016C,   // LCD1 T-Panel Setting Register [RESERVED]
    REG0170_HSSI_TX_PORT     = 0x0170,   // High Speed Serial Interface Tx Configuration Port Register [RESERVED]
    REG0174_HSSI_TX_MODE     = 0x0174,   // High Speed Serial Interface Tx Configuration Mode Register [RESERVED]
    REG0180_LCD2_HDP         = 0x0180,   // LCD2 Horizontal Display Period Register
    REG0184_LCD2_VDP         = 0x0184,   // LCD2 Vertical Display Period Register
    REG0188_LCD2_SERIAL      = 0x0188,   // LCD2 Serial Interface Setting Register
    REG018C_LCD2_PARALLEL    = 0x018C,   // LCD2 Parallel Interface Setting Register
    REG0190_LCD2_VSYNC_OUT   = 0x0190,   // LCD2 VSYNC Output Register
    REG0200_TVOUT_VSYNC_OUT  = 0x0200,   // TV-OUT Interface Clock Setting Register
    REG0204_TVOUT_HT         = 0x0204,   // TV-OUT Horizontal Total Register
    REG0208_TVOUT_HDP        = 0x0208,   // TV-OUT Horizontal Display Period Register
    REG020C_TVOUT_HDPS       = 0x020C,   // TV-OUT Horizontal Display Period Start Position Register
    REG0210_TVOUT_HP         = 0x0210,   // TV-OUT Horizontal Pulse (HSYNC) Width Register
    REG0218_TVOUT_VT         = 0x0218,   // TV-OUT Vertical Total Register
    REG021C_TVOUT_VDP        = 0x021C,   // TV-OUT Vertical Display Period Register
    REG0220_TVOUT_VDPS       = 0x0220,   // TV-OUT Vertical Display Period Start Position Register
    REG0224_TVOUT_FILD       = 0x0224,   // TV-OUT FILD Toggle Position Register
    REG0228_TVOUT_DATA_PORT  = 0x0228,   // TV-OUT Data Port Register
    REG022C_TVOUT_FRAME_XFER = 0x022C,   // TV-OUT Interface Frame Transfer Register
    REG0230_TVOUT_BLANK_DATA = 0x0230,   // TV-OUT Blank Data Register
    REG0300_GPIOP_CONFIG     = 0x0300,   // GPIOP Configuration Register
    REG0304_GPIOH_CONFIG_0   = 0x0304,   // GPIOH Configuration Register 0
    REG0308_GPIOH_CONFIG_1   = 0x0308,   // GPIOH Configuration Register 1
    REG030C_GPIOP_INPUT      = 0x030C,   // GPIOP Input Enable Register
    REG0310_GPIOH_INPUT_0    = 0x0310,   // GPIOH Input Enable Register 0
    REG0314_GPIOH_INPUT_1    = 0x0314,   // GPIOH Input Enable Register 1
    REG0318_GPIOP_PULLDOWN   = 0x0318,   // GPIOP Pull Down Control Register
    REG031C_GPIOH_PULLDOWN_0 = 0x031C,   // GPIOH Pull Down Control Register 0
    REG0320_GPIOH_PULLDOWN_1 = 0x0320,   // GPIOH Pull Down Control Register 1
    REG0324_GPIOP_STATUS     = 0x0324,   // GPIOP Status Register
    REG0328_GPIOH_STATUS_0   = 0x0328,   // GPIOH Status Register 0
    REG032C_GPIOH_STATUS_1   = 0x032C,   // GPIOH Status Register 1
    REG0330_GPIOP_POS_EDGE   = 0x0330,   // GPIOP Positive Edge Interrupt Trigger Register
    REG0334_GPIOH_POS_EDGE_0 = 0x0334,   // GPIOH Positive Edge Interrupt Trigger Register 0
    REG0338_GPIOH_POS_EDGE_1 = 0x0338,   // GPIOH Positive Edge Interrupt Trigger Register 1
    REG033C_GPIOP_NEG_EDGE   = 0x033C,   // GPIOP Negative Edge Interrupt Trigger Register
    REG0340_GPIOH_NEG_EDGE_0 = 0x0340,   // GPIOH Negative Edge Interrupt Trigger Register 0
    REG0344_GPIOH_NEG_EDGE_1 = 0x0344,   // GPIOH Negative Edge Interrupt Trigger Register 1
    REG0348_GPIOP_IRQ        = 0x0348,   // GPIOP Interrupt Status Register
    REG034C_GPIOH_IRQ_0      = 0x034C,   // GPIOH Interrupt Status Register 0
    REG0350_GPIOH_IRQ_1      = 0x0350,   // GPIOH Interrupt Status Register 1
    REG0400_HOST_CONFIG      = 0x0400,   // Host Interface Configuration Register
    REG0404_TE_CONFIG        = 0x0404,   // TE Configuration Register
    REG0408_MEM_ADDR_1       = 0x0408,   // Host Direct Memory Access Address Register 1
    REG040C_MEM_ADDR_0       = 0x040C,   // Host Direct Memory Access Address Register 0
    REG0410_MEM_PORT         = 0x0410,   // Host Direct Memory Access Port Register
    REG0414_MEM_STATUS       = 0x0414,   // Host Status Register [READONLY]
    REG0418_MEM_WRITE_PORT   = 0x0418,   // Host Memory Write Access Port Register [WRITEONLY]
    REG0420_MDDI_WRITE_PORT  = 0x0420,   // MDDI Memory Data Write Port Register [WRITEONLY,RESERVED]
    REG0480_OUTPUT_CLK       = 0x0480,   // Output Clock Register
    REG0484_VIDEO_IN_CONFIG  = 0x0484,   // Video Input Interface Configuration Register
    REG0488_VIDEO_IN_CTRL    = 0x0488,   // Video Input Interface Control Register
    REG048C_VIDEO_IN_STATUS  = 0x048C,   // Video Input Interface Status Register [READONLY]
    REG0490_MVI3_CONFIG_PORT = 0x0490,   // MVI3 Configuration Data Port Register
    REG0500_MEM_PATH_CONFIG  = 0x0500,   // Memory Write Path Configuration Register
    REG0504_MAIN_PATH_CONFIG = 0x0504,   // Main Memory Write Path Configuration Register
    REG0508_MAINA_RGBY_ADDR  = 0x0508,   // Main Memory BufferA RGB,Y Start Address Register
    REG050C_MAINA_UV_ADDR    = 0x050C,   // Main Memory BufferA UV Start Address Register
    REG0510_MAINB_RGBY_ADDR  = 0x0510,   // Main Memory BufferB RGB,Y Start Address Register
    REG0514_MAINB_UV_ADDR    = 0x0514,   // Main Memory BufferB UV Start Address Register
    REG0518_MAIN_MEM_STRIDE  = 0x0518,   // Main Memory Line Address Offset Register
    REG051C_MAIN_MEM_HEIGHT  = 0x051C,   // Main Memory Vertical Size Register
    REG0520_MAIN_IMG_WIDTH   = 0x0520,   // Main Image Horizontal Size Register
    REG0524_MAIN_IMG_HEIGHT  = 0x0524,   // Main Image Vertical Size Register
    REG0528_MAIN_IMG_XSTART  = 0x0528,   // Main Image X Start Position Register
    REG052C_MAIN_IMG_YSTART  = 0x052C,   // Main Image Y Start Position Register
    REG0580_SUB_PATH_CONFIG  = 0x0580,   // Sub Memory Write Path Config Register
    REG0584_SUBA_RGBY_ADDR   = 0x0584,   // Sub Memory BufferA RGB,Y Start Address Register
    REG0588_SUBA_UV_ADDR     = 0x0588,   // Sub Memory BufferA UV Start Address Register
    REG058C_SUBB_RGBY_ADDR   = 0x058C,   // Sub Memory BufferB RGB,Y Start Address Register
    REG0590_SUBB_UV_ADDR     = 0x0590,   // Sub Memory BufferB UV Start Address Register
    REG0594_SUB_MEM_STRIDE   = 0x0594,   // Sub Memory Line Address Offset Register
    REG0598_SUB_MEM_HEIGHT   = 0x0598,   // Sub Memory Vertical Size Register
    REG059C_SUB_IMG_WIDTH    = 0x059C,   // Sub Image Horizontal Size Register
    REG05A0_SUB_IMG_HEIGHT   = 0x05A0,   // Sub Image Vertical Size Register
    REG05A4_SUB_IMG_XSTART   = 0x05A4,   // Sub Image X Start Position Register
    REG05A8_SUB_IMG_YSTART   = 0x05A8,   // Sub Image Y Start Position Register
    REG0600_DISPLAY_MODE_0   = 0x0600,   // Display Mode Setting Register 0
    REG0604_DISPLAY_MODE_1   = 0x0604,   // Display Mode Setting Register 1
    REG0608_TRANS_ALPHA      = 0x0608,   // Transparency and Alpha Blend Control Register
    REG060C_BG_COLOR_1       = 0x060C,   // Background Color Setting Register 0
    REG0610_BG_COLOR_2       = 0x0610,   // Background Color Setting Register 1
    REG0614_ALPHA_RATIO      = 0x0614,   // Alpha Blend Ratio Setting Register
    REG0618_PIP1_TRANS_0     = 0x0618,   // PIP1 Window Transparency Key Color Register 0
    REG061C_PIP1_TRANS_1     = 0x061C,   // PIP1 Window Transparency Key Color Register 1
    REG0620_PIP2_TRANS_0     = 0x0620,   // PIP2 Window Transparency Key Color Register 0
    REG0624_PIP2_TRANS_1     = 0x0624,   // PIP2 Window Transparency Key Color Register 1
    REG0628_ALPHA_BLEND1_0   = 0x0628,   // Alpha Blend 1 Key Color Register 0
    REG062C_ALPHA_BLEND1_1   = 0x062C,   // Alpha Blend 1 Key Color Register 1
    REG0630_ALPHA_BLEND2_0   = 0x0630,   // Alpha Blend 2 Key Color Register 0
    REG0634_ALPHA_BLEND2_1   = 0x0634,   // Alpha Blend 2 Key Color Register 1
    REG0638_ALPHA_BLEND3_0   = 0x0638,   // Alpha Blend 3 Key Color Register 0
    REG063C_ALPHA_BLEND3_1   = 0x063C,   // Alpha Blend 3 Key Color Register 1
    REG0640_ALPHA_BLEND4_0   = 0x0640,   // Alpha Blend 4 Key Color Register 0
    REG0644_ALPHA_BLEND4_1   = 0x0644,   // Alpha Blend 4 Key Color Register 1
    REG0648_PSEUDO_SETTING   = 0x0648,   // Pseudo Setting Register
    REG064C_LUT_ADDR_COUNT   = 0x064C,   // LUT Address Counter Register
    REG0650_LUT_DATA_PORT    = 0x0650,   // LUT Data Port Register
    REG0680_MAIN_CTRL        = 0x0680,   // Main Window Control Register
    REG0684_MAIN1_MEM_SADDR  = 0x0684,   // Main1 Memory Start Address Register
    REG0688_MAIN1_MEM_STRIDE = 0x0688,   // Main1 Memory Line Address Offset Register
    REG068C_MAIN1_MEM_VSIZE  = 0x068C,   // Main1 Memory Vertical Size Register
    REG0690_MAIN1_IMG_HSIZE  = 0x0690,   // Main1 Image Horizontal Size Register
    REG0694_MAIN1_IMG_VSIZE  = 0x0694,   // Main1 Image Vertical Size Register
    REG0698_MAIN1_IMG_XSTART = 0x0698,   // Main1 Image X Start Position Register
    REG069C_MAIN1_IMG_YSTART = 0x069C,   // Main1 Image Y Start Position Register
    REG06A0_MAIN1_WIN_XSTART = 0x06A0,   // Main1 Window X Start Position Register
    REG06A4_MAIN1_WIN_YSTART = 0x06A4,   // Main1 Window Y Start Position Register
    REG06A8_MAIN2_MEM_SADDR  = 0x06A8,   // Main2 Memory Start Address Register
    REG06AC_MAIN2_MEM_STRIDE = 0x06AC,   // Main2 Memory Line Address Offset Register
    REG06B0_MAIN2_MEM_VSIZE  = 0x06B0,   // Main2 Memory Vertical Size Register
    REG06B4_MAIN2_IMG_HSIZE  = 0x06B4,   // Main2 Image Horizontal Size Register
    REG06B8_MAIN2_IMG_VSIZE  = 0x06B8,   // Main2 Image Vertical Size Register
    REG06BC_MAIN2_IMG_XSTART = 0x06BC,   // Main2 Image X Start Position Register
    REG06C0_MAIN2_IMG_YSTART = 0x06C0,   // Main2 Image Y Start Position Register
    REG06C4_MAIN2_WIN_XSTART = 0x06C4,   // Main2 Window X Start Position Register
    REG06C8_MAIN2_WIN_YSTART = 0x06C8,   // Main2 Window Y Start Position Register
    REG0700_PIP1_CTRL        = 0x0700,   // PIP1 Window Control Register
    REG0704_PIP1_SCALE_MODE  = 0x0704,   // PIP1 Window Scaling Mode Register
    REG0708_PIP1_HORZ_SCALE  = 0x0708,   // PIP1 Window Horizontal Scale Register
    REG070C_PIP1_VERT_SCALE  = 0x070C,   // PIP1 Window Vertical Scale Register
    REG0710_PIP1_ADAPT_SCALE = 0x0710,   // PIP1 Adaptive Scaling Parameter Register [RESERVED]
    REG0714_PIP1_RGBY_ADDR1  = 0x0714,   // PIP1 Memory BufferA RGB,Y Start Address Register
    REG0718_PIP1_UV_ADDR1    = 0x0718,   // PIP1 Memory BufferA UV Start Address Register
    REG071C_PIP1_RGBY_ADDR2  = 0x071C,   // PIP1 Memory BufferB RGB,Y Start Address Register
    REG0720_PIP1_UV_ADDR2    = 0x0720,   // PIP1 Memory BufferB UV Start Address Register
    REG0724_PIP1_MEM_STRIDE  = 0x0724,   // PIP1 Memory Line Address Offset Register
    REG0728_PIP1_MEM_VSIZE   = 0x0728,   // PIP1 Memory Vertical Size Register
    REG072C_PIP1_IMG_HSIZE   = 0x072C,   // PIP1 Image Horizontal Size Register
    REG0730_PIP1_IMG_VSIZE   = 0x0730,   // PIP1 Image Vertical Size Register
    REG0734_PIP1_IMG_XSTART  = 0x0734,   // PIP1 Image X Start Position Register
    REG0738_PIP1_IMG_YSTART  = 0x0738,   // PIP1 Image Y Start Position Register
    REG073C_PIP1_WIN_XSTART  = 0x073C,   // PIP1 Window X Start Position Register
    REG0740_PIP1_WIN_YSTART  = 0x0740,   // PIP1 Window Y Start Position Register
    REG0744_PIP1_WIN_XEND    = 0x0744,   // PIP1 Window X End Position Register
    REG0748_PIP1_WIN_YEND    = 0x0748,   // PIP1 Window Y End Position Register
    REG074C_PIP1_SCALE_ADDR  = 0x074C,   // PIP1 Window Scaler Port Address Counter Control Register
    REG0750_PIP1_SCALE_PORT  = 0x0750,   // PIP1 Window Scaler Coefficient Table Access Port Register [WRITEONLY]
    REG0800_PIP2_CTRL        = 0x0800,   // PIP2 Window Control Register
    REG0804_PIP2_SCALE_MODE  = 0x0804,   // PIP2 Window Scaling Mode Register
    REG0808_PIP2_HORZ_SCALE  = 0x0808,   // PIP2 Window Horizontal Scale Register
    REG080C_PIP2_VERT_SCALE  = 0x080C,   // PIP2 Window Vertical Scale Register
    REG0810_PIP2_ADAPT_SCALE = 0x0810,   // PIP2 Adaptive Scaling Parameter Register [RESERVED]
    REG0814_PIP2_RGBY_ADDR1  = 0x0814,   // PIP2 Memory BufferA RGB,Y Start Address Register
    REG0818_PIP2_UV_ADDR1    = 0x0818,   // PIP2 Memory BufferA UV Start Address Register
    REG081C_PIP2_RGBY_ADDR2  = 0x081C,   // PIP2 Memory BufferB RGB,Y Start Address Register
    REG0820_PIP2_UV_ADDR2    = 0x0820,   // PIP2 Memory BufferB UV Start Address Register
    REG0824_PIP2_MEM_STRIDE  = 0x0824,   // PIP2 Memory Line Address Offset Register
    REG0828_PIP2_MEM_VSIZE   = 0x0828,   // PIP2 Memory Vertical Size Register
    REG082C_PIP2_IMG_HSIZE   = 0x082C,   // PIP2 Image Horizontal Size Register
    REG0830_PIP2_IMG_VSIZE   = 0x0830,   // PIP2 Image Vertical Size Register
    REG0834_PIP2_IMG_XSTART  = 0x0834,   // PIP2 Image X Start Position Register
    REG0838_PIP2_IMG_YSTART  = 0x0838,   // PIP2 Image Y Start Position Register
    REG083C_PIP2_WIN_XSTART  = 0x083C,   // PIP2 Window X Start Position Register
    REG0840_PIP2_WIN_YSTART  = 0x0840,   // PIP2 Window Y Start Position Register
    REG0844_PIP2_WIN_XEND    = 0x0844,   // PIP2 Window X End Position Register
    REG0848_PIP2_WIN_YEND    = 0x0848,   // PIP2 Window Y End Position Register
    REG084C_PIP2_PANA_SCALE  = 0x084C,   // PIP2 Panorama Area A Scale Register
    REG0850_PIP2_PANB_SCALE  = 0x0850,   // PIP2 Panorama Area B Scale Register
    REG0854_PIP2_PAN1_START  = 0x0854,   // PIP2 Panorama Area 1 Start Position Register
    REG0858_PIP2_PAN2_START  = 0x0858,   // PIP2 Panorama Area 2 Start Position Register
    REG085C_PIP2_PAN3_START  = 0x085C,   // PIP2 Panorama Area 3 Start Position Register
    REG0860_PIP2_PAN4_START  = 0x0860,   // PIP2 Panorama Area 4 Start Position Register
    REG0864_PIP2_PAN_DELTA   = 0x0864,   // PIP2 Linear Panorama Area Delta Register
    REG0868_PIP2_SCALE_ADDR  = 0x0868,   // PIP2 Window Scaler Port Address Counter Control Register
    REG086C_PIP2_SCALE_PORT  = 0x086C,   // PIP2 Window Scaler Coefficient Table Access Port Register [WRITEONLY]
    REG0900_AME_CTRL         = 0x0900,   // AME Control Register
    REG0904_AME_PARAM_ADJUST = 0x0904,   // AME Parameter Adjust Register
    REG0908_AME_INPUT_WIDTH  = 0x0908,   // AME Input Image Width Register
    REG090C_AME_INPUT_HEIGHT = 0x090C,   // AME Input Image Height Register
    REG0910_AME_HORZ_START   = 0x0910,   // AME Processing Horizontal Start Position Register
    REG0914_AME_HORZ_END     = 0x0914,   // AME Processing Horizontal End Position Register
    REG0918_AME_VERT_START   = 0x0918,   // AME Processing Vertical Start Position Register
    REG091C_AME_VERT_END     = 0x091C,   // AME Processing Vertical End Position Register
    REG0920_AME_SVERT_START  = 0x0920,   // AME Sampling Area Vertical Start Position Register
    REG0924_AME_SHOR_START   = 0x0924,   // AME Sampling Area Horizontal Start Position Register
    REG0928_AME_SAMP_SIZE    = 0x0928,   // AME Sampling Area Size Register
    REG092C_AME_SAMP_P1      = 0x092C,   // AME Sampling Area Parameter 1 Register
    REG0930_AME_SAMP_P2      = 0x0930,   // AME Sampling Area Parameter 2 Register
    REG0A00_IRQ_STATUS       = 0x0A00,   // Interrupt Status Register [READONLY]
    REG0A04_IRQ_ENABLE       = 0x0A04,   // Interrupt Enable Register
    REG0A08_IRQ_CLEAR_ASSERT = 0x0A08,   // Interrupt Clear Assert Register [RESERVED]
    REG0B00_I2C_CLK_DIVISOR  = 0x0B00,   // I2C Clock Divisor Register
    REG0B04_I2C_ENABLE       = 0x0B04,   // I2C Enable Register
    REG1040_MDDI_WAKE_MODE   = 0x1040,   // MDDI LCD Wake Mode Signal Select Register
    REG1048_MDDI_FIFO_ERROR  = 0x1048,   // MDDI Client Interface FIFO Error Status/Clear Register
    REG1050_MDDI_DATA_RATE   = 0x1050,   // MDDI Data Rate Register
    REG1054_MDDI_CAPABILITY  = 0x1054,   // MDDI Client Capability Register
    REG1060_IMEM_WRITE_PORT  = 0x1060,   // Indirect Memory Write Access Port Address Register

    REGFLAG_BASE             = 0xFFF0,   // Special reserved flags from here to REGFLAG_END_OF_TABLE

    REGFLAG_WAIT_DRAM        = 0xFFFB,   // WAIT FOR DRAM READY
    REGFLAG_WAIT_PLL         = 0xFFFC,   // WAIT FOR PLL READY
    REGFLAG_REGISTER_UPDATE  = 0xFFFD,   // UPDATE REGISTERS (updates appropriate Register Update bitfields)
    REGFLAG_END_OF_TABLE     = 0xFFFF    // END OF REGISTERS MARKER
} eReg;

RAPH800 Initialization table (Hitachi):

.data:9A2A1F30                 mddi_reg_val <0x30, 0>  ; 0
.data:9A2A1F30                 mddi_reg_val <0x20, 0x303C>; 1
.data:9A2A1F30                 mddi_reg_val <0x24, 0x401A>; 2
.data:9A2A1F30                 mddi_reg_val <0x28, 0x31A>; 3
.data:9A2A1F30                 mddi_reg_val <0x2C, 1>  ; 4
.data:9A2A1F30                 mddi_reg_val <0xFFFC, 1>; 5  -- Wait for 0x2c & 0x100
.data:9A2A1F30                 mddi_reg_val <0x84, 0x215>; 6
.data:9A2A1F30                 mddi_reg_val <0x88, 0x38>; 7
.data:9A2A1F30                 mddi_reg_val <0x8C, 0x2113>; 8
.data:9A2A1F30                 mddi_reg_val <0x90, 0>  ; 9
.data:9A2A1F30                 mddi_reg_val <0x2C, 2>  ; 10
.data:9A2A1F30                 mddi_reg_val <0xFFFB, 1>; 11  -- Wait for 0x94 & 0x1
.data:9A2A1F30                 mddi_reg_val <0x2C, 3>  ; 12
.data:9A2A1F30                 mddi_reg_val <0x100, 0x3702>; 13
.data:9A2A1F30                 mddi_reg_val <0x104, 0x380>; 14
.data:9A2A1F30                 mddi_reg_val <0x140, 0x3E>; 15
.data:9A2A1F30                 mddi_reg_val <0x144, 0xEF>; 16
.data:9A2A1F30                 mddi_reg_val <0x148, 7> ; 17
.data:9A2A1F30                 mddi_reg_val <0x14C, 5> ; 18
.data:9A2A1F30                 mddi_reg_val <0x150, 0> ; 19
.data:9A2A1F30                 mddi_reg_val <0x154, 0x293>; 20
.data:9A2A1F30                 mddi_reg_val <0x158, 0x27F>; 21
.data:9A2A1F30                 mddi_reg_val <0x15C, 0xA>; 22
.data:9A2A1F30                 mddi_reg_val <0x160, 5> ; 23
.data:9A2A1F30                 mddi_reg_val <0x164, 0> ; 24
.data:9A2A1F30                 mddi_reg_val <0x168, 0xE3>; 25
.data:9A2A1F30                 mddi_reg_val <0x180, 0x57>; 26
.data:9A2A1F30                 mddi_reg_val <0x184, 0xDB>; 27
.data:9A2A1F30                 mddi_reg_val <0x188, 0xE3>; 28
.data:9A2A1F30                 mddi_reg_val <0x18C, 0> ; 29
.data:9A2A1F30                 mddi_reg_val <0x190, 0> ; 30
.data:9A2A1F30                 mddi_reg_val <0x200, 0xA6>; 31
.data:9A2A1F30                 mddi_reg_val <0x204, 0> ; 32
.data:9A2A1F30                 mddi_reg_val <0x208, 0x13F>; 33
.data:9A2A1F30                 mddi_reg_val <0x20C, 0> ; 34
.data:9A2A1F30                 mddi_reg_val <0x210, 0> ; 35
.data:9A2A1F30                 mddi_reg_val <0x214, 0> ; 36
.data:9A2A1F30                 mddi_reg_val <0x218, 0> ; 37
.data:9A2A1F30                 mddi_reg_val <0x21C, 0x1DF>; 38
.data:9A2A1F30                 mddi_reg_val <0x220, 0> ; 39
.data:9A2A1F30                 mddi_reg_val <0x224, 0> ; 40
.data:9A2A1F30                 mddi_reg_val <0x400, 0x8000>; 41
.data:9A2A1F30                 mddi_reg_val <0x480, 0x4001>; 42
.data:9A2A1F30                 mddi_reg_val <0x484, 0x62>; 43
.data:9A2A1F30                 mddi_reg_val <0x500, 0> ; 44
.data:9A2A1F30                 mddi_reg_val <0x504, 0x8000>; 45
.data:9A2A1F30                 mddi_reg_val <0x508, 0> ; 46
.data:9A2A1F30                 mddi_reg_val <0x50C, 0> ; 47
.data:9A2A1F30                 mddi_reg_val <0x510, 0> ; 48
.data:9A2A1F30                 mddi_reg_val <0x514, 0> ; 49
.data:9A2A1F30                 mddi_reg_val <0x518, 0x1E>; 50
.data:9A2A1F30                 mddi_reg_val <0x51C, 0x9F>; 51
.data:9A2A1F30                 mddi_reg_val <0x520, 0x1DF>; 52
.data:9A2A1F30                 mddi_reg_val <0x524, 0x27F>; 53
.data:9A2A1F30                 mddi_reg_val <0x528, 0> ; 54
.data:9A2A1F30                 mddi_reg_val <0x52C, 0> ; 55
.data:9A2A1F30                 mddi_reg_val <0xFFFD, 0x10>; 56  -- ORR  [0x500], [0x500], 0x10
.data:9A2A1F30                 mddi_reg_val <0x580, 0> ; 57
.data:9A2A1F30                 mddi_reg_val <0x584, 0> ; 58
.data:9A2A1F30                 mddi_reg_val <0x588, 0xD2C>; 59
.data:9A2A1F30                 mddi_reg_val <0x58C, 0xFA0>; 60
.data:9A2A1F30                 mddi_reg_val <0x590, 0x10CC>; 61
.data:9A2A1F30                 mddi_reg_val <0x594, 0x34>; 62
.data:9A2A1F30                 mddi_reg_val <0x598, 0x77>; 63
.data:9A2A1F30                 mddi_reg_val <0x59C, 0x13F>; 64
.data:9A2A1F30                 mddi_reg_val <0x5A0, 0xEF>; 65
.data:9A2A1F30                 mddi_reg_val <0x5A4, 0> ; 66
.data:9A2A1F30                 mddi_reg_val <0x5A8, 0> ; 67
.data:9A2A1F30                 mddi_reg_val <0xFFFD, 0x20>; 68  -- ORR  [0x500], [0x500], 0x20
.data:9A2A1F30                 mddi_reg_val <0x600, 0> ; 69
.data:9A2A1F30                 mddi_reg_val <0x604, 0x101>; 70
.data:9A2A1F30                 mddi_reg_val <0x608, 0> ; 71
.data:9A2A1F30                 mddi_reg_val <0x60C, 0x80>; 72
.data:9A2A1F30                 mddi_reg_val <0x610, 0> ; 73
.data:9A2A1F30                 mddi_reg_val <0x648, 0> ; 74
.data:9A2A1F30                 mddi_reg_val <0x680, 0x8000>; 75
.data:9A2A1F30                 mddi_reg_val <0x684, 0> ; 76
.data:9A2A1F30                 mddi_reg_val <0x688, 0x1E>; 77
.data:9A2A1F30                 mddi_reg_val <0x68C, 0x9F>; 78
.data:9A2A1F30                 mddi_reg_val <0x690, 0x1DF>; 79
.data:9A2A1F30                 mddi_reg_val <0x694, 0x27F>; 80
.data:9A2A1F30                 mddi_reg_val <0x698, 0> ; 81
.data:9A2A1F30                 mddi_reg_val <0x69C, 0> ; 82
.data:9A2A1F30                 mddi_reg_val <0x6A0, 0> ; 83
.data:9A2A1F30                 mddi_reg_val <0x6A4, 0> ; 84
.data:9A2A1F30                 mddi_reg_val <0x6A8, 0> ; 85
.data:9A2A1F30                 mddi_reg_val <0x6AC, 0x34>; 86
.data:9A2A1F30                 mddi_reg_val <0x6B0, 0x77>; 87
.data:9A2A1F30                 mddi_reg_val <0x6B4, 0x12B>; 88
.data:9A2A1F30                 mddi_reg_val <0x6B8, 0x31>; 89
.data:9A2A1F30                 mddi_reg_val <0x6BC, 0xF>; 90
.data:9A2A1F30                 mddi_reg_val <0x6C0, 0xF0>; 91
.data:9A2A1F30                 mddi_reg_val <0x6C4, 0> ; 92
.data:9A2A1F30                 mddi_reg_val <0x6C8, 0x96>; 93
.data:9A2A1F30                 mddi_reg_val <0x700, 0> ; 94
.data:9A2A1F30                 mddi_reg_val <0x704, 0x20A>; 95
.data:9A2A1F30                 mddi_reg_val <0x708, 0x400>; 96
.data:9A2A1F30                 mddi_reg_val <0x70C, 0x400>; 97
.data:9A2A1F30                 mddi_reg_val <0x714, 0xC00>; 98
.data:9A2A1F30                 mddi_reg_val <0x718, 0xD2C>; 99
.data:9A2A1F30                 mddi_reg_val <0x71C, 0xFA0>; 100
.data:9A2A1F30                 mddi_reg_val <0x720, 0x10CC>; 101
.data:9A2A1F30                 mddi_reg_val <0x724, 0x14>; 102
.data:9A2A1F30                 mddi_reg_val <0x728, 0x3B>; 103
.data:9A2A1F30                 mddi_reg_val <0x72C, 0x63>; 104
.data:9A2A1F30                 mddi_reg_val <0x730, 0x63>; 105
.data:9A2A1F30                 mddi_reg_val <0x734, 0> ; 106
.data:9A2A1F30                 mddi_reg_val <0x738, 0> ; 107
.data:9A2A1F30                 mddi_reg_val <0x73C, 0x32>; 108
.data:9A2A1F30                 mddi_reg_val <0x740, 0x32>; 109
.data:9A2A1F30                 mddi_reg_val <0x744, 0x95>; 110
.data:9A2A1F30                 mddi_reg_val <0x748, 0x95>; 111
.data:9A2A1F30                 mddi_reg_val <0x800, 0> ; 112
.data:9A2A1F30                 mddi_reg_val <0x804, 0x20A>; 113
.data:9A2A1F30                 mddi_reg_val <0x808, 0x400>; 114
.data:9A2A1F30                 mddi_reg_val <0x80C, 0x400>; 115
.data:9A2A1F30                 mddi_reg_val <0x814, 0xC00>; 116
.data:9A2A1F30                 mddi_reg_val <0x818, 0xD2C>; 117
.data:9A2A1F30                 mddi_reg_val <0x81C, 0xFA0>; 118
.data:9A2A1F30                 mddi_reg_val <0x820, 0x10CC>; 119
.data:9A2A1F30                 mddi_reg_val <0x824, 0x14>; 120
.data:9A2A1F30                 mddi_reg_val <0x828, 0x3B>; 121
.data:9A2A1F30                 mddi_reg_val <0x82C, 0x63>; 122
.data:9A2A1F30                 mddi_reg_val <0x830, 0x63>; 123
.data:9A2A1F30                 mddi_reg_val <0x834, 0x64>; 124
.data:9A2A1F30                 mddi_reg_val <0x838, 0x64>; 125
.data:9A2A1F30                 mddi_reg_val <0x83C, 0x64>; 126
.data:9A2A1F30                 mddi_reg_val <0x840, 0x64>; 127
.data:9A2A1F30                 mddi_reg_val <0x844, 0xC7>; 128
.data:9A2A1F30                 mddi_reg_val <0x848, 0xC7>; 129
.data:9A2A1F30                 mddi_reg_val <0x900, 0> ; 130
.data:9A2A1F30                 mddi_reg_val <0x904, 0> ; 131
.data:9A2A1F30                 mddi_reg_val <0x908, 0x13F>; 132
.data:9A2A1F30                 mddi_reg_val <0x90C, 0xEF>; 133
.data:9A2A1F30                 mddi_reg_val <0x910, 0> ; 134
.data:9A2A1F30                 mddi_reg_val <0x914, 0x13F>; 135
.data:9A2A1F30                 mddi_reg_val <0x918, 0> ; 136
.data:9A2A1F30                 mddi_reg_val <0x91C, 0xEF>; 137
.data:9A2A1F30                 mddi_reg_val <0xFFFD, 0xC000>; 138  -- ORR  [0x600], [0x600], 0x8000
.data:9A2A1F30                 mddi_reg_val <0xB00, 3> ; 139
.data:9A2A1F30                 mddi_reg_val <0x300, 0x203F>; 140
.data:9A2A1F30                 mddi_reg_val <0x304, 0> ; 141
.data:9A2A1F30                 mddi_reg_val <0x308, 0> ; 142
.data:9A2A1F30                 mddi_reg_val <0x30C, 0x5FFF>; 143
.data:9A2A1F30                 mddi_reg_val <0x310, 0x7FFF>; 144
.data:9A2A1F30                 mddi_reg_val <0x314, 0xFF>; 145
.data:9A2A1F30                 mddi_reg_val <0x318, 0x7FC0>; 146
.data:9A2A1F30                 mddi_reg_val <0x31C, 0xFFFF>; 147
.data:9A2A1F30                 mddi_reg_val <0x320, 0xFF>; 148
.data:9A2A1F30                 mddi_reg_val <0x324, 0x7FFF>; 149
.data:9A2A1F30                 mddi_reg_val <0x328, 0> ; 150
.data:9A2A1F30                 mddi_reg_val <0x32C, 0> ; 151

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